Motorola Corporation

Kla-tencor Technologies Corporation

Kla Tencor Corporation

Faivel S Pintchovski

Robert W Fiordalice

Wilson D Calvert

Papu D Maniar

John R Yeargain

Peter H Kessler

Sergey D Lopatin

Igor C Ivanov

Artur Kolics

Philip J Tobin

Jenn-Hwa Huang

Stanley Michael Filipiak

Schyi-Yi Wu

Wen Zhong Kong

A method of forming an electrically conductive via. A first electrically conductive layer is formed, and a second layer is formed on the first layer. The second layer has desired barrier layer properties. A third non electrically conductive layer is formed on the second layer. A via hole is etched through the third layer, thereby exposing a portion of the second layer at the bottom of the via hole. The exposed portion of the second layer at the bottom of the via hole is redistributed so that at least a portion of the second layer is removed from the bottom of the via hole and deposited on lower portions of the sidewalls of the via hole. A fourth electrically conductive layer is formed within the via hole to form the electrically conductive via.

Barrier material formation in integrated circuit structures

An integrated circuit and a method of manufacturing an integrated circuit is provided including providing an integrated circuit having a trench and via provided in a dielectric layer. A nano-electrode-array is formed over the dielectric layer in the trench and via, and a conductor is deposited over the nano-electrode-array. The conductor and the nano-electrode-array are coplanar with a surface of the dielectric layer.

Nano-electrode-array for integrated circuit interconnects

Barrier enhancement

An improved contact structure and process for forming an improved contact structure for a semiconductor device. A metal (14) is formed on a first metal layer (12) positioned on a substrate (10) The metal (14) is a Group VIIB or Group VIII metal or metal oxide and increases the electrically conductive surface area (25) of the first metal layer (12). In one embodiment, a Group VIIB or Group VIII metal layer is deposited onto the first metal layer and the Group VIIB or Group VIII metal layer is anisotropically etched to form sidewall spacers (24). An insulating layer (16) is deposited overlying the first conductive layer (12) and the sidewall spacers (24). A via opening (18) is formed in the insulation layer (16) to expose a portion of the electrically conductive surface area (25). A second metal layer (22) fills the opening (18) and forms a metallurgical contact to the first metal layer (12).

Method of making a contact structure

A process for fabricating a metallization structure includes the formation of an interlayer (20) using an MOCVD deposition process. A metal-organic precursor, having as one component tungsten, is used to deposit the interlayer (20) onto a surface region (18) of a substrate (10) at the bottom of an opening (16). The MOCVD deposition process forms a conformal layer which evenly coats all surfaces of the opening (16). Next, a refractory metal layer (22) is deposited to overlie the interlayer (20). Because of conformal nature of the MOCVD deposition process, refractory metal layer can be formed using corrosive gasses such as tungsten hexafluoride.

Process for fabricating a metallization structure in a semiconductor

Self-aligned HFETS are fabricated by providing a semi-insulating substrate and forming a low bandgap III-V semiconductor layer thereon. A first dielectric layer of a first dielectric material is formed on the III-V layer and first and second openings are formed through the first dielectric layer and the III-V layer. After forming dielectric spacers of a second dielectric material on the sidewalls of the first and second openings, gates are formed therein. The first dielectric layer is subsequently removed and source and drain regions are formed in the III-V layer and substrate adjacent to each of the gates. The formation of the source and drain regions is self-aligned to the gates. After forming isolation regions between devices, ohmic contacts to the source and drain regions, all being of a like material, are formed. This formation is also self-aligned to the gates.

Self-aligned complementary HFETS

The present invention includes a process for forming an intermetallic layer over a semiconductor substrate and a device formed by the process. The intermetallic layer includes a material having a molecular formula of AB.sub.3, wherein A is an element having an atomic number of 39-41 or 57-73 and B is an element having an atomic of 45, 46, 77, or 78. In one process, an intermetallic member is formed by forming a patterned layer including the A or B element over a substrate, depositing a layer of the other element, and reacting them. The process forms a self-aligned member. Chemical-mechanical polishing, ion milling, and a lift-off method may be performed to pattern an AB.sub.3 intermetallic layer. In a device, an intermetallic member may act as a gate electrode, an electrode of a capacitor, a conductive spacer, an interconnect, or a contact or via plug. An almost endless number of devices may be formed with the intermetallic members.

Process for forming an intermetallic member on a semiconductor substrate

A method is provided for forming a material layer in a semiconductor device using liquid phase deposition. A material layer such as a metal layer, a dielectric layer, a semiconductor layer or a superconducting layer is deposited by the liquid-phase thermal decomposition of a metal-organic precursor dissolved in an anhydrous organic solvent. The organic solvent has a chemical polarity corresponding to the selected metal-organic precursor and has a normal boiling point above the decomposition temperature of the selected precursor. As a result of few restrictions on the range of precursor physical properties, the present invention enables the use of a wide variety of molecular compositions which can be used for the formation of an equally wide variety of material layers. In one embodiment of the invention, a semiconductor substrate is subjected to a liquid mixture comprising a metal-substituted heterocyclic acetylacetonate precursor dissolved in tetradecane (b.p. 254.degree.C.). Depending upon the structure of the acetylacetonate, either a metal or a metal oxide film is deposited in the liquid phase on a semiconductor substrate immersed in a solution which is maintained at the decomposition temperature of the acetylacetonate precursor.

Method for forming a material layer in a semiconductor device using

A solid source chemical vapor deposition apparatus and a CVD method for fabricating semiconductor devices are disclosed. In accordance with the process for fabricating semiconductor devices, a CVD reactor chamber having a solid reactant source apparatus coupled thereto is provided. The reactant source apparatus includes a container which can be heated in a controllable manner and which has a gas diffuser located in the container. The container is provided with gas input and output which are located so that a carrier gas can be passed through the gas diffuser and through a finely divided solid reactant source material which is positioned over the gas diffuser. The carrier gas together with any vapor derived from the solid reactant source material is conveyed from the outlet of the reactant source apparatus to the CVD reactor chamber. Semiconductor substrates are positioned in the CVD reaction chamber, are heated, and are subjected to the carrier gas and the source vapor to deposit a layer of the source material on the substrates.

Process for fabricating semiconductor devices using a solid reactant

A process for fabricating an improved semiconductor device is disclosed wherein a protective layer of Al.sub.2 O.sub.3 is selectively formed to encapsulate a refractory-metal conductor. To form the Al.sub.2 O.sub.3 layer, first an Al/refractory-metal alloy is selectively formed on the surface of the refractory-metal conductor, then the Al/refractory-metal alloy is reacted with O.sub.2. The resulting Al.sub.2 O.sub.3 encapsulation layer acts as an O.sub.2 diffusion barrier preventing the oxidation of the refractory-metal during subsequent process steps used to fabricate the semiconductor device. In addition, the Al.sub.2 O.sub.3 layer improves the mechanical compatibility of the refractory-metal conductor with other materials used to construct the semiconductor device, such as, for example, improving the adhesion of an overlying layer of passivation glass to the refractory-metal conductor.

Process for the selective encapsulation of an electrically conductive

A method is disclosed for fabricating a semiconductor device and especially for contacting a semiconductor device. A silicon substrate is provided which has a device region formed at the surface thereof and which is contacted with a silicide. An insulating layer overlies the substrate and has an opening therethrough which exposes a portion of that device region. Titanium nitride is deposited in a blanket layer overlying the silicide and the insulating layer. A leveling agent such as a spin-on glass is applied to the structure to substantially fill the opening. That leveling agent is then anisotropically etched to leave the leveling agent only in the opening. The leveling agent is used as an etch mask to remove the portion of titanium nitride which is located outside the opening. After removing the remaining leveling agent, the titanium nitride in the opening is used as a nucleating surface for the selective deposition of a tungsten plug which fills the contact opening. The titanium nitride layer serves as both a nucleating surface and as a barrier layer which separates the tungsten from the underlying silicon.

Method for making a w/tin contact

A quick-release multiple gas injection pipe connector fitting for removable attachment to a gas reaction chamber having a plurality of gas injection passages. The fitting permits a number of gas inlet lines to be removed from or attached to a reaction chamber fixture in one operation without a separate removal or attachment step for each gas line. The fitting also facilitates a process where the reaction gases are preferably mixed only at the reaction site and not before.

Multiple gas injection apparatus for LPCVD equipment

A heat exchanger apparatus having two sleeves which fit together to seal a sinuous heat exchange fluid channel between them where the channel is open along its length prior to assembly. The sleeves may be made removable to permit easy cleaning of the heat exchange fluid channel. The heat exchange fluid channel may thus be directly cleaned along its entire length in contrast to conventional heat exchangers employing tubes, where the tube interior can be accessed only from the ends. In one embodiment, the channel has a rectangular cross-section to enhance the heat exchange capability of the apparatus.

Heat exchange apparatus for high temperature LPCVD equipment

A process for selective formation of a titanium silicide, TiSi.sub.2, layer at high temperatures and low pressures via chemical vapor deposition during semiconductor device manufacturing. At 700.degree. to 1000.degree. C. and 0.5 to 1.5 torr, TiSi.sub.2 deposits only on exposed silicon or polysilicon surfaces and not at all on neighboring silicon dioxide. The process provides an excellent means of providing low resistivity interconnects without a mask step or subsequent annealing and removal of unreacted titanium.

Growing community of inventors

Austin, TX, United States of America

Faivel S Pintchovski