Stmicroelectronics (crolles 2) Sas

Stmicroelectronics S.a.

Centre National De La Recherche Scientifique

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Stmicroelectronics (rousset) Sas

Fady Abouzeid

Sylvain Clerc

Philippe Roche

Gilles Gasiot

Bastien Giraud

Jean-Philippe Noel

Yvain Thonnart

Guenole Lallement

Jean-Pierre Schoellkopf

Dimitri Soussan

Victor Malherbe

Martin Cochet

Fabian Firmin

Capucine Lecat-Mathieu De Boissac

Patrik Temleitner

A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.

Ionizing radiation detector

Absorbed ionizing particles differentially effect first and second acquiring circuit stages configured to respectively generate first and second acquisition signals. Each acquisition signal has a characteristic that is variable as a function of an amount of absorbed ionizing particles. A measuring circuit generates, on the basis of the first and second acquisition signals, a relative parameter indicative of a relationship between the variable characteristics. A computation of a total ionizing dose is made using a 1st- or 2nd-degree polynomial relationship in the relative parameter.

Device for measuring doses of ionizing particles

A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.

Measurement of the duration of a pulse

A digital circuit includes logic circuitry formed by logic gates. Each logic gate includes a p-channel MOSFET and an n-channel MOSFET. A body bias generator circuit applies an n-body bias voltage to the n-body bias nodes of the p-channel MOSFETs and applies a p-body bias voltage to the p-body bias nodes of the n-channel MOSFETs. The body bias generator circuit operates in: a first mode to apply a ground supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply a positive supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage; and a second mode to apply the positive supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply the ground supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage.

Body biasing for ultra-low voltage digital circuits

A multi-stage ring oscillator generates an output clock signal having a frequency which is dependent on a digitally leakage current that is applied to each stage of the multi-stage ring oscillator. A magnitude of a leakage current sourced by each digitally controlled leakage current source is set by a control circuit in response to a selection signal. A calibration circuit processes a reference clock signal and the output clock signal generated by the multi-stage ring oscillator to make adjustment to the selection signal which drives a locking of a frequency of the output clock signal to a desired frequency.

Leakage-based oscillator with digital correction

A flip-flop includes a pulse-generator and a pulse-controlled latch. The pulse generator includes a first inverter to invert a clock signal, a second inverter to invert the inverted clock signal to generate a delayed clock signal, and a NOR gate having a first input coupled to an output of the first inverter, a second input coupled to the output of the second inverter, and an output, which, in operation, provides a pulse signal in response to a rising edge of a received clock signal. The pulse-controlled latch circuit has a data input and is controlled by the pulse signal and the delayed clock signal. The flip-flop may include a multiplexer to select an input signal.

Pulsed semi-dynamic fast flip-flop with scan

A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference ('BGPD') of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

Method for controlling an integrated circuit

An integrated with a block including first and second oppositely doped semiconductor wells. There are standard cells placed next to one another, each standard cell including first transistors and a clock tree cell encircled by standard cells. The clock tree cell has a third semiconductor well with the same doping type as the doping of the first well and second transistors. The clock tree cell also has a semiconductor strip extending continuously around the third well and having the opposite doping type to the doping of the third well to electrically isolate the third well from the first well.

Integrated circuit comprising a clock tree cell

The invention relates to an integrated circuit comprising: The integrated circuit comprises an electrical power supply network () able to apply separate electrical biases directly to the first and second ground planes.

A device and a method for controlling an SRAM-type device, including: a bistable circuit and two switching circuits respectively connecting two access terminals of the bistable circuit to two complementary bit lines in a first direction, each switching circuit including a first switch and a second switch in series between one of the bit lines and one of the access terminals, the control terminal of the second switch being connected to a word control line in the first direction; and a third switch between the midpoint of the series connection and a terminal of application of a reference potential, a control terminal of the third switch being connected to the other one of the access terminals.

SRAM read-write memory cell having ten transistors

A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.

Read boost circuit for memory device

A flip-flop may include a first master stage for latching data, a second slave stage for latching data, and an input multiplexer circuit receiving, as input, data to be latched in the flip-flop. The multiplexer may have single clock phase. The first master stage may be clocked based upon a clock phase, whereas the second stage may be clocked based upon another clock phase.

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Grenoble, France

Fady Abouzeid