Qualcomm Incorporated

Fadoua Chafik

Anil Chowdary Kota

Samit Sengupta

Xiaochen Zhang

Disclosed are apparatuses and techniques for fabricating an apparatus including a semiconductor device. The semiconductor device may include one or more static random-access memory (SRAM) transistors, each including a first gate spacer structure; one or more logic nominal transistors, each including a second gate spacer structure; and one or more logic gate-biased transistors, each including a third gate spacer structure, where the third gate spacer structure is thinner than the first gate spacer structure and where the one or more SRAM transistors, the one or more logic nominal transistors, and the one or more logic gate-biased transistors each have a same contacted poly pitch (CPP).

Gate spacer structures for three-dimensional semiconductor devices

A method for repairing logic design includes inserting primary logic gates in a primary logic design path of a logic chip. The method also includes inserting alternative logic gates in an alternate logic design path of the logic chip. The alternate logic design path and the primary logic design path are coupled to multiple fuses. The potentially defective design is repaired by selecting between the alternate logic design path and the primary logic design path with the fuses when the logic design is defective.

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San Diego, CA, United States of America

Fadoua Chafik