University of California

King Abdullah University of Science and Technology

Morpho Technologies

Unist-academy Industry Research Corporation

Finlasin Technology LLC

Fadi Joseph Kurdahi

Ahmed Mohamed Eltawil

Mohammed Fouda

Muhammad Sayed Khairy Abdelghaffar

Behzad Mohebbi

Khaled Nabil Salama

Aditi Majumder

Mohammed Affan Zidan

Magda El Zarki

Zhiying Wang

Su Gil Lee

Jong Eun Lee

Kiarash Amiri

Gi Ju Jung

Amin Khajeh

Shih-Hsien Yang

Hasan Erdem Yantir

Ming-Hau Lee

Amr M A Hussein

Marwen Zorgui

Ahmed Mohamed Ahmed Eltawil

Behzad Barjesteh Mohebbi

A stuck-at fault mitigation method for resistive random access memory (ReRAM)-based deep learning accelerators, includes: confirming a distorted output value (Y0) due to a stuck-at fault (SAF) by using a correction data set in a pre-trained deep learning network, by means of ReRAM-based deep learning accelerator hardware; updating an average (&#x3bc;) and a standard deviation (&#x3c3;) of a batch normalization (BN) layer by using the distorted output value (Y0), by means of the ReRAM-based deep learning accelerator hardware; folding the batch normalization (BN) layer in which the average (&#x3bc;) and the standard deviation (&#x3c3;) are updated into a convolution layer or a fully-connected layer, by means of the ReRAM-based deep learning accelerator hardware; and deriving a normal output value (Y1) by using the deep learning network in which the batch normalization (BN) layer is folded, by means of the ReRAM-based deep learning accelerator hardware.

Stuck-at fault mitigation method for ReRAM-based deep learning accelerators

Disclosed are various approaches for a controller that can generate and use non-stationary polar codes for encoding and decoding information. In one example, a method includes performing, by an encoder of the controller, a linear operation on at least one vector of information to be stored in a memory. The linear operation includes generating a polar encoded representation from the at least one vector of information. The linear operation also includes generating an output using at least one permutation that is based on a statistical characterization analysis of channels of the memory and a channel dependent permutation that is applied to the polar encoded representation. In some aspects, the statistical characterization analysis includes a respective reliability level of each one of the plurality of channels, and the channel dependent permutation includes an ordered permutation that orders the channels according to their respective reliability level.

Non-stationary polar codes for resistive memories

Various examples are provided examples related to resistive content addressable memory (RCAM) based in-memory computation architectures. In one example, a system includes a content addressable memory (CAM) including an array of cells having a memristor based crossbar and an interconnection switch matrix having a gateless memristor array, which is coupled to an output of the CAM. In another example, a method, includes comparing activated bit values stored a key register with corresponding bit values in a row of a CAM, setting a tag bit value to indicate that the activated bit values match the corresponding bit values, and writing masked key bit values to corresponding bit locations in the row of the CAM based on the tag bit value.

Resistive content addressable memory based in-memory computation architecture

A power management technique utilizing a method for accurately and rapidly estimating the change in the statistical distribution of data at each block in a communication system leading to or originating from a memory that is experiencing voltage scaling induced errors is disclosed. An appropriate memory supply voltage that maximizes power savings is found by exploiting the available SNR slack while keeping system performance within a required margin.

Cognitive power management for communication systems

A method of audio and video synchronization may include capturing an image by each of a plurality of cameras. The images and audio may be compared with each other for synchronization.

Video frame synchronization for a federation of projectors using camera feedback

A method and arrangement for reducing power consumption in an M row&#xd7;N column array of processing cells. A row mask register masks individual cells in each row for being enabled. A column mask register masks individual cells in each column for being enabled. The combination of the row mask register signal and column mask register signal enables or disables each cell of the array. Enabled cells are activated to execute an operation or function, while disabled cells a prevented from consuming dynamic power. Depending on the application and enabled cells thereby, power consumption is reduced.

Power saving method and arrangement for a configurable processor array

A circuit employing an array of reconfigurable processing elements for wireless baseband processing. The circuit includes a first linear array of reconfigurable processing elements for processing signals from a first channel, and a second linear array of reconfigurable processing elements, coupled in parallel with the first linear array of reconfigurable processing elements, for processing signals from a second channel that is concurrent with the first channel. The circuit also includes a frame buffer array having a number of frame buffers that corresponds to a number of reconfigurable processing elements in the first and second linear arrays of processing elements. A point-to-point data bus is connected between each reconfigurable processor and an associated frame buffer. A shared data bus is connected between the first and second linear arrays of reconfigurable processing elements and the frame buffer array.

Digital signal processor for wireless baseband processing

Growing community of inventors

Irvine, CA, United States of America

Fadi Joseph Kurdahi