Inphi Corporation

Clariphy Communications, Inc.

Facundo Abel Alcides Ramos

Mario Rafael Hueda

Damian Alfonso Morero

Matias German Schnidrig

Oscar Ernesto Agazzi

Diego Ernesto Crivelli

Hugo Santiago Carrer

Norman L Swenson

Vadim Gutnik

Paul Voois

Ramiro Rogelio Lopez

Martin Ignacio Del Barco

Jorge Manuel Finochietto

Alfredo Javier Taddei

Mauro Marcelo Bruni

Federico Nicolas Paredes

Elvio Adrian Serrano

Martin Carlos Asinari

Pablo Gustavo Quiroga

Roman Antonio Arenas

Alejandro Javier Schwoykoski

Adrián Ulises Morales

María Laura Ferster

Mario Alejandro Castrillon

Maria Laura Ferster

Ulises Morales

Laura Maria Ferster

Teodoro Ariel Goette

A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Coherent transceiver architecture

A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

A decoder performs forward error correction based on quasi-cyclic regular column-partition low density parity check codes. A method for designing the parity check matrix reduces the number of short-cycles of the matrix to increase performance. An adaptive quantization post-processing technique further improves performance by eliminating error floors associated with the decoding. A parallel decoder architecture performs iterative decoding using a parallel pipelined architecture.

Non-concatenated FEC codes for ultra-high speed optical transport networks

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Cordoba, Argentina

Facundo Abel Alcides Ramos