Stmicroelectronics S.r.l.

Stmicroelectronics Gmbh

Stmicroelectronics S.a.

Fabrizio Simone Rovati

Danilo Pietro Pau

Emiliano Mario Piccinelli

Andrea Lorenzo Vitali

Daniele Alfonso

Antonio Borneo

Luigi Della Torre

Daniele Bagni

Gianluca Filippini

William P Robbins

Luca Fanucci

Pierluigi Gardella

Daniele Sirtori

Luca Celetto

Luca Pezzoni

Sergio Saponara

Howard Gurney

Andrew MacCormack

Bruno Biffi

Roberta Bruni

Anna Valsasna

Elio Privitera

Angelo Schiavone

Emiliano Mario Angelo Piccinelli

Andrea Cenciotti

Antonio Maria Borneo

Paolo Sergio Zambotti

Pascal Jean Mellot

In an embodiment, a method for converting an input video sequence, comprising digital images organized in frames and operating at a variable frame-rate, into an output video sequence, operating at a pre-set constant frame-rate, storing the input video sequence temporarily and controlling fetching of images of said temporarily stored input video sequence. The method further includes controlling fetching of images from the temporarily stored input video sequence by adjusting an emptying rate to form an intermediate video sequence; and carrying out an operation of motion-compensated interpolation on the intermediate video sequence to form the output video sequence operating at a pre-set constant frame-rate, the emptying rate being adjusted as a function of a number of images of the input video sequence with variable frame-rate temporarily stored. An application is in the reproduction of video sequences in mobile terminals, with the capacity of audio-video conversation, for example for videoconferences.

Method for the frame-rate conversion of a video sequence of digital images, related apparatus and computer program product

A processing system, such as typically a CPU, is used for converting a digital signal organized in pixels, such as a video signal, between a first format and a second multiple-description format. The system comprises at least one input register and at least one output register, and is configured via instructions, that can be constituted at least in part by instructions of a SIMD type, so as to: order the pixels of the signal to be converted in a set of input registers; and take selectively the pixels from the aforesaid set of input registers and place them in an orderly way in at least one output register.

Method and system for the treatment of multiple-description signals, and corresponding computer-program product

A method for encoding and decoding media signals, includes the operations of generating at a transmitting side multiple descriptions associated to data of the media signals through a downsampling operation performed on the data, and decoding at a receiving side the multiple descriptions for reconstructing the data by merging the multiple descriptions. The operation of generating multiple descriptions further includes the operations of obtaining a spectral representation of the data, including bands associated to different ranges, the bands being obtained by a suitable quantization operation and including at least one highly quantized band, that is subjected to a higher degree of quantization. A scrambling operation is performed on the spectral representation by moving the at least one highly quantized band to a different range, the scrambling operation being performed prior the downsampling operation. In decoding, a descrambling operation is performed before the merging operation on the multiple descriptions.

Methods and system for encoding/decoding signals including scrambling spectral representation and downsampling

In an embodiment of a method for converting an input video sequence, comprising digital images organized in frames and operating at a variable frame-rate, into an output video sequence, operating at a pre-set constant frame-rate, it is envisaged to store the input video sequence temporarily and to control fetching of images of said temporarily stored input video sequence. The method moreover envisages: 

Programs having a given instruction-set architecture are executed on a multiprocessor system comprising a plurality of processors, for example of a VLIW type, each of said processors being able to execute, at each processing cycle, a respective maximum number of instructions. The instructions are compiled as instruction words of given length executable on a first processor. At least some of the instruction words of given length are converted into modified-instruction words executable on a second processor. The operation of modifying comprises in turn at least one operation chosen in the group consisting of: splitting the instruction words into modified-instruction words; and entering no-operation instructions in the modified-instruction words.

Process for running programs on processors and corresponding processor system

Transcoder apparatus for transcoding an input video bit-stream having a first encoding profile (e.g., MPEG-2) into an output video bit-stream having a second encoding profile (e.g., H.264), the first encoding profile including motion estimation information, the apparatus including: a front-end for extracting the motion estimation information from the input video bit-stream, and a back-end for constructing the output bit-stream. The front-end and the back-end of the apparatus are interconnected (e.g., via a buffer) to pass the motion estimation information from the front-end to the back-end, thereby avoiding motion estimation in constructing the output bit-stream at the apparatus back-end.

Method for transcoding compressed video signals, related apparatus and computer program product therefor

A moving-image signal, such as typically a luminance signal organized in blocks of pixels is coded via a technique that envisages the steps of: comparing a block to be coded with a plurality of candidate prediction blocks; determining, for each candidate prediction block, a respective value of an index representing the difference between the block to be coded and each candidate prediction block; and choosing between the candidate prediction blocks, as a function of the respective value of the aforesaid index, a prediction block to be used for coding of the block to be coded. The signal is sampled pixel by pixel on the block to be coded and on the plurality of candidate prediction blocks, thus generating respective surfaces representing the pattern of the signal in the block to be coded and in the candidate prediction blocks. Chosen as an index is an index of the parallelism between the aforesaid respective surfaces.

Method and system for coding moving image signals, corresponding computer program product

The method for encoding and/or decoding video signals, includes the operations of generating at a transmitter side a multiple descriptions vector associated to a pixel values vector of the video signals and decoding at a receiver side available descriptions vector for reconstructing the pixel values vector. The operation of generating a multiple descriptions vector includes the steps of obtaining the pixel values vector by selecting a group of pixels in a picture of the video signal and applying an encoding matrix to the pixel values vector. The decoding operation includes the step of applying a decoding matrix that is in an inverse relationship with the encoding matrix to the available descriptions vector to obtain the pixel values vector.

Method for encoding/decoding signals with multiple descriptions vector and matrix

The present invention relates to the demultiplexing of a digital data stream in a receiver so as to retain only those parts of the digital data stream required by the receiver. Such demultiplexing is particularly useful when applied to a receiver circuit in a television system having a digital set-top-box. A memory in the receiver stores packet identifiers of data packets required by the receiver, which are stored in the memory under the control of a first control circuit. A second control circuit extracts packet identifiers from incoming data packets in an input digital data stream. A third control circuit receives the extracted packet identifier and determines whether this matches one of the packet identifiers stored in the memory. A match signal is set by the third control circuit to the second control circuit responsive to a match. The second control circuit demultiplexes the input data packet responsive to the match signal.

Digital receiver demultiplexer

A spatial-type de-interlacing process to be applied to a digital image for obtaining a spatial reconstruction. Furthermore, to the digital image there are also applied one or more temporal-type motion compensation de-interlacing processes for obtaining one or more temporal reconstructions, and the spatial reconstruction and the one or more temporal reconstructions are sent to a decision module. The decision module applies a cost function to the spatial reconstruction and the temporal reconstructions and chooses from among the spatial reconstruction and the temporal reconstructions the one that minimizes the cost function. Preferential application is to display systems, in particular displays of a cathode-ray type, liquid-crystal type, and plasma type which use a mechanism of progressive scan.

Method and system for de-interlacing digital images, and computer program product therefor

The program to be executed is compiled by translating it into native instructions of the instruction-set architecture of the processor system, organizing the instructions deriving from the translation of the program into respective bundles in an order of successive bundles, each bundle grouping together instructions adapted to be executed in parallel by the processor system. The bundles of instructions are ordered into respective sub-bundles, said sub-bundles identifying a first set of instructions, which must be executed before the instructions belonging to the next bundle of said order, and a second set of instructions, which can be executed both before and in parallel with respect to the instructions belonging to said subsequent bundle of said order. There is defined a sequence of execution of the instructions in successive operating cycles of the processor system, assigning each sub-bundle to an operating cycle, thus preventing simultaneous assignment to the same operating cycle of two sub-bundles belonging to the first set of two successive bundles. The instructions of the sequence may be executed by the various processors of the system in conditions of binary compatibility.

Process for running programs with selectable instruction length processors and corresponding processor system

A system for generating motion vectors in a motion estimator is configured for co-operating with an engine for calculating estimation error for generating motion vectors, according to estimation errors and/or motion vectors previously generated. The system comprises a program memory that contains program data for a motion-estimation algorithm, and a motion-vector memory that contains data identifying said motion vectors previously calculated. The system further comprises an arithmetic and logic unit co-operating with the program memory and motion-vector memory to generate motion vectors in a programmable way to get them to correspond, for example, to predictors deriving from motion-estimation operations already performed on the macroblocks of the reference frame or on the previous macroblocks of the current frame, as updates calculated using the co-ordinates of the motion vectors already issued for the current macroblock, or as absolute motion vectors, generated as such, taking the components directly from the program code.

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Milan, Italy

Fabrizio Simone Rovati