Stmicroelectronics (rousset) Sas

Stmicroelectronics S.a.

Stmicroelectronics (grenoble 2) Sas

Stmicroelectronics (alps) Sas

Stmicroelectronics S.r.l.

Proton World International N.v.

Stmicroelectronics Gmbh

Fabrice Romain

Denis Farison

Yannick Teglia

Fabrice Marinet

Christophe Laurencin

Mathieu Pierre Lisart

Pierre-Yvan Liardet

Rene Peyrard

Alain C Pomet

Patrick Arnould

Sylvie Wuidart

Jean-Louis Modave

Guido Marco Bertoni

Michael Peeters

Pasqualina Fragneto

Guy Monier

Denis Cottin

Bernard Plessier

Romain Palmade

Fabio Sozzani

Christophe Mani

Christophe Eichwald

Yveline Guilloux

Christophe Cataldo

Laurence Sirtori

Sophie Gabriele

Brigitte Hennebois

Marie-No&euml;lle Lepareux

Pierre Yvan Liardet

Jean-Michel Derien

An output potential level among two first levels is delivered according to an input level among two second levels. The output potential level is delivered at a first node connecting together first and second transistors electrically in series between two second nodes of application of the first levels. A first DC voltage defining a high limit for the control voltage of the first transistor is delivered by a first voltage generator powered by one of the second nodes. A second DC voltage defining a high limit for the control voltage of the second transistor is delivered by a second voltage generator controlled by a value representative of the first voltage and powered between the second nodes.

Level shifting device and method

A method includes processing, by an arithmetic and logic unit of a processor, masked data, and keeping, by the arithmetic and logic unit of the processor, the masked data masked throughout their processing by the arithmetic and logic unit. A processor includes an arithmetic and logic unit configured to keep masked data masked throughout processing of the masked data in the arithmetic and logic unit.

Processor and method for processing mask data

The present disclosure relates to a circuit and method for determining a sign indicator bit of a binary datum including a step for processing of the binary datum masked with a masking operation, and not including any processing step of the binary datum.

Circuit and method for binary flag determination

A method for detecting a reading error of a datum in memory. A binary word which is representative of the datum and an error correcting or detecting code is read by: reading a first part of the binary word stored at a first address in a first memory circuit; and reading a second part of the binary word stored at a second address in a second memory circuit. The first and second parts read from the first and second memory circuits, respectively, are concatenated to form a read binary word. The datum is then obtained by removing the error correcting or detecting code from the read binary word. A new error correcting or detecting code is calculated from the obtained datum and compared to the removed error correcting or detecting code to detect error in the obtained datum.

Error detection

An embodiment method for determining a carry digit indicator bit of a first binary datum includes a step for processing of the first binary datum masked by a masking operation, and not including any processing step of the first binary datum.

Device and method for binary flag determination

A method for detecting a writing error of a datum in memory includes: storing at least two parts of equal size of a binary word representative of said datum at the same address in at least two identical memory circuits, and comparing internal control signals of the two memory circuits to determine existence of the writing error.

The present description concerns an electronic device including: a modulator-demodulator circuit; a first integrated circuit implementing a first subscriber identification module; and at least one second integrated circuit intended to implement a second subscriber identification module, wherein a sequencing terminal of the first circuit and a sequencing terminal of the second circuit are connected to a same sequencing terminal of the modulator-demodulator circuit.

Electronic device

A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.

The present disclosure concerns a memory access control system comprising: a processing device capable of operating in a plurality of operating modes, and of accessing a memory using a plurality of address aliases; and a verification circuit configured: to receive, in relation with a first read operation of a first memory location in the memory, an indication of a first of said plurality of address aliases associated with the first read operation; to verify that a current operating mode of the processing device permits the processing device to access the memory using the first address alias; to receive, during the first read operation, a first marker stored at the first memory location; and to verify, based on the first marker and on the first address alias, that the processing device is permitted to access the first memory location.

Memory access control and verification using address aliasing and markers

In order to verify the authenticity of a product associated with a host device, the product contains, in segments of a non-volatile memory, several different functions stored in ciphered fashion. The host device sends a control signal for selecting and activating one of those ciphered functions. The product then deciphers and executes the function. The result of the function execution is then enciphered and communicated back to host device when a decision on product authenticity is made.

Method for verifying the authenticity of a product

The authenticity of a product associated with a host device is verified through a process. The product contains, in segments of a non-volatile memory, several different functions stored in ciphered fashion. The process involves, in a first phase, the sending by the host device of a control signal for executing a function, with the product functioning to decipher the function and store the unciphered function in the non-volatile memory. The process further involves, in a second phase, the sending by the host device of a control signal for causing execution of the deciphered function, with the product functioning to execute the function and send a result of this execution back to the host device. The host device evaluates the received result to verify product authenticity.

Mechanism for verifying the authenticity of a product

In order to verify the authenticity of a product associated with a host device, the product contains, in segments of a non-volatile memory, several different functions stored in ciphered fashion. The host device sends a control signal for selecting and activating one of those ciphered functions. The product then deciphers and executes the function. The result of the function execution is then communicated back to host device when a decision on product authenticity is made.

Growing community of inventors

Rians, France

Fabrice Romain