Stmicroelectronics (rousset) Sas

Stmicroelectronics S.a.

Proton World International N.v.

Stmicroelectronics (alps) Sas

Stmicroelectronics Belgium

Fabrice Marinet

Pascal Fornara

Jean-Louis Modave

Michael Peeters

Mathieu Pierre Lisart

Alexandre Sarafianos

Jimmy Fort

Alexandre Malherbe

Denis Farison

Julien Mercier

Pierre-Yvan Liardet

Philippe Candelier

Benjamin Duval

Thomas Ordas

Ronny Van Keer

Gilles Van Assche

Stephane Denorme

Joel Damiens

Stephane Chesnais

Luc Wuidart

Sylvie Wuidart

Julien Delalleau

Alain C Pomet

Fabien Journet

Jérôme Tournemille

Camille Botella

Marc Benveniste

An electronic device includes processing circuitry and one or more memories, including a non-volatile memory. Ephemeral cryptographic key generation circuitry, in operation, applies a function to code stored in the non-volatile memory, generating an ephemeral cryptographic key. Cryptographic circuitry coupled between the processing circuitry and the one or more memories, in operation, performs one or more cryptographic operations on data using the generated ephemeral cryptographic key. The device may include a register, which, in operation, temporarily stores the generated ephemeral cryptographic key.

Encryption and/or decryption key device, system and method

An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.

Method for protecting data stored in a memory, and corresponding integrated circuit

A method of authenticating a first electronic circuit includes generating a first signature using the first electronic circuit, the generating of the first signature being based on states of a plurality of electric nodes distributed within the first electronic circuit. A second signature is generated using a second electronic circuit, the generating of the second signature being based on states of a plurality of electric nodes distributed within the second electronic circuit. The first signature is compared to the second signature. The first electronic circuit is authenticated based on the comparison of the first signature to the second signature.

Authentication method and circuit

The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.

Processor authentication method

Authenticating a device using processing circuitry that generates fingerprints based on states of a plurality of nodes that are coupled to a plurality of circuits. A first fingerprint is generated at a first time based on first states of the plurality of nodes. A second fingerprint is generated at a second time based on second states of the plurality of nodes, the first fingerprint influencing the second states. Electronic data is obtained from the device to be authenticated. The electronic data is compared with a fingerprint generated and a determination whether to authorize operation of the device is made based on a result of the comparison.

One-way function

The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and at least one previously-executed opcode.

A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.

Electronic chip memory

A semiconductor substrate has a front face and a back face. A first contact and a second contact, spaced apart from each other, are located on the front face. An electrically conductive wafer is located on the back face. A detection circuit is configured to detect a thinning of the substrate from the back face. The detection circuit including a measurement circuit that takes a measurement of a resistive value of the substrate between said at least one first contact, said at least one second contact and said electrically conductive wafer. Thinning is detected in response to the measured resistive value.

Method for detecting an attempt to breach the integrity of a semiconductor substrate of an integrated circuit from its back face, and corresponding integrated circuit

Processor authentication method through signed instruction

An integrated circuit includes a circuit module storing sensitive data. An electrically conductive body at a floating potential is located in the integrated circuit and holds an initial amount of electric charge. In response to an attack attempting to access the sensitive data, electric charge is collected on the electrically conductive body. A protection circuit is configured to ground an output of the circuit module, and thus preclude access to the sensitive data, in response to collected amount of electric charge on the electrically conductive body differing from the initial amount and exceeding a threshold.

Method for protecting an integrated circuit module using an antifuse, and corresponding device

An electronic circuit includes an interface, a read-only memory in which encrypted data are stored, and cryptographic circuitry coupled to the interface. In operation, the cryptographic circuitry uses a decryption key received via the interface to decrypt the encrypted data. The electronic circuit performs one or more operations using the decrypted data.

Electronic circuit

An integrated circuit is protected against at attack. An electrically conductive body at floating potential is situated in the integrated circuit. The electrically conductive body has an initial amount of electric charge prior to the attack and functions to collect electric charge as a result of the attack. A detection circuit operates to detect an amount of electric charge collected on the electrically conductive body and determine whether the collected amount is different from the initial amount. If the detected amount of charge is different from the initial amount, a control circuit trigger the taking of a protective action.

Method for protecting an integrated circuit, and corresponding device

An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.

Growing community of inventors

Chateauneuf le Rouge, France

Fabrice Marinet