S.o.i.tec Silicon on Insulator Technologies

S.o.i. Tec Silicon on Insulator Technologies, S.a.

Soitec

Commissariat a L'energie Atomique

Commissariat À L'energie Atomique (Cea)

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Exagan

S.o.i. Tec Silicon

Fabrice Letertre

Bruno Ghyselen

Olivier Rayssac

Bruce Faure

Eric Jalaguier

Hubert Moriceau

Carlos Mazure

Michael Ragan Krames

Nathan Fredrick Gardner

Alice Boussagol

Pierre Rayssac, Legal Representative

Bernard Aspar

Oleg Kononchuk

Christophe Maleville

Christophe Morales

Pascal Guenard

Melvin B McLaurin

Thibaut Maurice

Gisèle Rayssac, Legal Representative

Yves Mathieu Le Vaillant

Chantal Arena

Sébastien Kerdiles

Jean-Marc Bethoux

Sèbastien Kerdiles

Didier Landru

Ionut Radu

Chrystel Deguet

Laurent Guillot

Konstantin Bourdelle

Ian Cayrefourcq

Robert Baptist

Léa Di Cioccio

Marek Kostrzewa

Oliver Rayssac

Elsa Hugonnard-Bruyere

Robert Langer

Giséle Rayssac, Legal Representative

Fredéric Metral

Domenico Lo Verde

Chris Werkhoven

Oleg Kononchuck

Mike Krames

Nelson Mclaurin

Nate Gardner

Melvin B Mclaurin

Chrystal Deguet

Bruce Fauvre

Yves Mathieu Levaillant

The invention relates to a method for fabricating a pseudo-substrate comprising the steps of providing a single crystal ingot, providing a handle substrate, cutting a thin slice from the single crystal ingot, and attaching the thin slice to the handle substrate to form a pseudo-substrate. According to the invention, the thickness of the thin slice is substantially equal or inferior to a critical thickness below which the slice, if taken alone, is no longer mechanically stable. The invention further relates to a semiconductor structure.

Pseudo-substrate with improved efficiency of usage of single crystal material

An integrated circuit includes a first chip including a high-voltage depletion-mode transistor and a second chip including an enhancement-mode device. The chips have first and second gate contact pads, first and second source contact pads and first and second drain contact pads, respectively, on their front sides. Chips are joined together via their front sides, and the area of the first chip is larger than that of the second chip. The first chip includes an additional contact pad on its front side that is electrically insulated from the high-voltage depletion-mode transistor and that contacts the second gate contact pad. The first gate contact pad contacts the second source contact pad and/or the first source contact pad contacts the second drain contact pad. The first gate contact pad and the additional contact pad extend at least partially into a peripheral portion of the first chip.

Integrated circuit formed from a stack of two series-connected chips

The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes providing a support that includes a barrier layer thereon for preventing loss by diffusion of elements derived from dissociation of the support at epitaxial growth temperatures; providing a seed layer on the barrier layer, wherein the seed layer facilitates epitaxial growth of a single crystal III-nitride semiconductor layer thereon; epitaxially growing a nitride working layer on the thin seed layer; and removing the support to form the semiconductor substrate.

Fabrication of substrates with a useful layer of monocrystalline semiconductor material

A method for the formation of an at least partially relaxed strained material layer, comprises providing a seed substrate; patterning the seed substrate; growing a strained material layer on the patterned seed substrate; transferring the strained material layer from the patterned seed substrate to an intermediate substrate; and at least partially relaxing the strained material layer by a heat treatment.

Relaxation and transfer of strained material layers

An automatic cutting device is described for cutting an assembly. The assembly includes a material having a weakened zone therein that defines a useful layer and being attached to a source substrate. The cutting device includes a cutting mechanism and a holding and positioning mechanism operatively associated with the cutting mechanism. The holding and positioning mechanism positions the material so that the cutting mechanism detaches the layer from the source substrate along the weakened zone. The cutting device also includes a control mechanism for adjusting at least two different portions of the assembly during detachment of the layer to facilitate a more precise detachment.

Substrate cutting device and method

The invention relates to a process for fabricating a semiconductor that comprises providing a handle substrate comprising a seed substrate and a weakened sacrificial layer covering the seed substrate; joining the handle substrate with a carrier substrate; optionally treating the carrier substrate; detaching the handle substrate at the sacrificial layer to form the semiconductor structure; and removing any residue of the sacrificial layer present on the seed substrate.

Process for fabricating a semiconductor structure employing a temporary bond

A heterostructure that includes, successively, a support substrate of a material having an electrical resistivity of less than 10ohm&#xb7;cm and a thermal conductivity of greater than 100 W&#xb7;m&#xb7;K, a bonding layer, a first seed layer of a monocrystalline material of composition AlInGaN, a second seed layer of a monocrystalline material of composition AlInGaN, and an active layer of a monocrystalline material of composition AlInGaN, and being present in a thickness of between 3 and 100 micrometers. The materials of the support substrate, the bonding layer and the first seed layer are refractory at a temperature of greater than 750&#xb0; C., the active layer and second seed layer have a difference in lattice parameter of less than 0.005 &#x212b;, the active layer is crack-free, and the heterostructure has a specific contact resistance between the bonding layer and the first seed layer that is less than or equal to 0.1 ohm&#xb7;cm.

Heterostructure for electronic power components, optoelectronic or photovoltaic components

A process for manufacturing a stacked structure comprising at least one thin layer bonded to a target substrate, in which a thin layer is formed by introduction gaseous species into an initial substrate, to form a weakened layer separating a film from the rest of the initial substrate, a first contact face of the thin layer is bonded to a face of an intermediate substrate by molecular adhesion, and the initial substrate is fractured at the weakened layer so as to expose a free face of the thin layer. The intermediate substrate is then removed in order to obtain the stacked structure.

Manufacturing process for a stacked structure comprising a thin layer bonding to a target substrate

Composite substrates are produced that include a strained III-nitride material seed layer on a support substrate. Methods of producing the composite substrate include developing a desired lattice strain in the III-nitride material to produce a lattice parameter substantially matching a lattice parameter of a device structure to be formed on the composite substrate. The III-nitride material may be formed with a Ga polarity or an N polarity. The desired lattice strain may be developed by forming a buffer layer between the III-nitride material and a growth substrate, implanting a dopant in the III-nitride material to modify its lattice parameter, or forming the III-nitride material with a coefficient of thermal expansion (CTE) on a growth substrate with a different CTE.

Strain engineered composite semiconductor substrates and methods of forming same

A method of fabricating a device by providing an auxiliary substrate having a metal nitride layer disposed thereon where the nitride layer has a nitrogen face and an opposite face and a dislocation density that is less than about 10, with the nitrogen face of the nitride layer facing the auxiliary substrate; depositing at least one epitaxial nitride layer on the exposed opposite face of the nitride layer of the structure; depositing a further metal layer over at least a portion of the epitaxial nitride layer(s); bonding a final substrate on the deposited metal layer; and removing the auxiliary substrate to form the device from the final substrate and deposited layers. Preferably, the device that is formed includes a LED or laser.

Optoelectronic substrate and methods of making same

The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes transferring a seed layer on to a support substrate; and depositing a working layer on the seed layer to form a composite substrate. The seed layer is made of a material that accommodates thermal expansion of the support substrate and of the working layer. In another embodiment, the method includes providing a source substrate with a weakened zone defining a nucleation layer, bonding a support substrate to the source substrate, detaching the nucleation layer and support substrate at the weakened zone by applying laser irradiation stress, depositing a semiconductor material upon the nucleation layer, bonding a target substrate to the deposited layer and removing the support substrate and nucleation layer. The result is a semiconductor substrate that includes the layer of semiconductor material on a support or target substrate.

The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least partially relaxed strained material islands to the target substrate. The at least partial relaxation is facilitated by the presence of low-viscosity or compliant layers adjacent to the strained material layer. The invention also provides semiconductor structures having an at least partially relaxed strained material layer, and semiconductor devices fabricated using an at least partially relaxed strained material layer.

Methods for relaxation and transfer of strained layers and structures fabricated thereby

Methods of fabricating relaxed layers of semiconductor materials include forming structures of a semiconductor material overlying a layer of a compliant material, and subsequently altering a viscosity of the compliant material to reduce strain within the semiconductor material. The compliant material may be reflowed during deposition of a second layer of semiconductor material. The compliant material may be selected so that, as the second layer of semiconductor material is deposited, a viscosity of the compliant material is altered imparting relaxation of the structures. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Methods of fabricating semiconductor structures and devices are also disclosed. Novel intermediate structures are formed during such methods. Engineered substrates include a plurality of structures comprising a semiconductor material disposed on a layer of material exhibiting a changeable viscosity.

Methods of forming relaxed layers of semiconductor materials, semiconductor structures, devices and engineered substrates including same

Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.

Semiconductor structures and devices including semiconductor material on a non-glassy bonding layer

Growing community of inventors

Grenoble, France

Fabrice Letertre