Upmem

Brison S.a.

Fabrice Devaux

Jean-François Roy

Renaud Ayrignac

David Furodet

Gilles Hamou

The invention relates to a memory device comprising: —DRAM memory circuits (), the total capacity of which is divided into a first part () and a second part () larger than the first part (); —a control circuit configured to access the memory circuits, the control circuit comprising: —a first block () configured to execute a first algorithm (A) intended to protect the first part () from a row-hammering effect; —a second block () configured to execute a second algorithm (A) intended to protect the second part () from a row-hammering effect that may occur, the second algorithm (A) using a main table stored in the first part ().

Memory device provided with dram memory circuits arranged in such a way as to minimize the size of a memory block allowing management of the row-hammering

A calculation system comprises a computing device having one or more instruction-controlled processing cores and a memory controller, the memory controller including a cache memory; and a memory circuit coupled to the memory controller via a data bus and an address bus, the memory circuit being adapted to have a first m-bit memory location accessible by a plurality of first addresses provided on the address bus, the calculation device being configured to select, in order to each memory operation accessing the first m-bit memory location, one address among the plurality first addresses.

Methods and devices for bypassing the internal cache of an advanced DRAM memory controller

A method of protecting a DRAM memory device from the row hammer effect, the memory device comprising a plurality of banks composed of memory rows, may be implemented by at least one logic prevention device configured to respectively associate contiguous sections of rows of a bank with sub-banks. The prevention logic is also configured to execute a preventive refresh cycle of the sub-banks that is entirely executed before the number of rows activated in a sub-bank exceed a critical hammer value. A DRAM memory device, a buffer circuit or a controller of such a memory may comprise the logic for preventing the row hammer effect.

Method and circuit for protecting a DRAM memory device from the row hammer effect

A memory device comprises one or more bank(s), each bank comprising a plurality of DRAM memory rows, the memory device further comprising: an external access port configured to allow an external memory controller to activate and then access the memory rows of each bank; one or more internal processor(s) capable of activating and then accessing the memory rows of each bank; a logic for detecting triggering of the Row Hammer configured to monitor, for each bank, the activation commands from the external memory controller and from one or more internal processor(s), the logic for detecting triggering including memory storage and a logic for sending preventive refresh configured to implement a refresh operation for one or more of the adjacent rows of each identified row by emitting refresh requests instead of the periodic refresh requests generated by the external memory controller, delaying one or more of said periodic refresh requests.

Row hammer correction logic for dram with integrated processor

A computer device comprises a first processor; a plurality of memory circuits, a first one of which comprises one or more other processors; a data bus coupling the first processor to each of the memory circuits, each of the memory circuits having a data port with a width of m bits and the data bus having a width of n bits, n being higher than m, the first processor and/or another circuit being suitable for reading or writing the data value of n bits in the first memory circuit by converting a first address into a plurality of second addresses corresponding to memory locations of m bits in the first memory circuit, and by performing the reading or writing operation of the data value of n bits in the first memory circuit over a plurality of memory access operations.

Computing device within memory processing and narrow data ports

A method of protecting a DRAM memory device from the row hammer effect includes the memory device comprising a plurality of banks composed of memory rows, the method being implemented by at least one logic prevention device configured to respectively associate contiguous sections of rows of a bank with sub-banks and to execute, on each activation of a row of a sub-bank (b) of the memory, an increment step of a required number of preventive refreshments (REFRESH_ACC; REFRESH_ACC/PARAM_D) of the sub-bank (b) using an activation threshold (PARAM_D) of the sub-bank (b). The prevention logic is also configured to execute a preventive refresh sequence of the sub-banks according to their required number of preventive refreshes. A DRAM memory device, a buffer circuit or a controller of such a memory may comprise the logic for preventing the row hammer effect.

A processor core comprising in its set of instructions, a combined addition and bound-checking instruction (ADDCK) defining an integer n implicitly, or explicitly as a parameter of the instruction; an adder having a width p strictly greater than n bits; and a processing circuit (MUX, 42) designed to respond to the combined instruction by activating an overflow signal (BX) when the adder generates a carry of rank n during the addition of operands of width p.

Combined instruction for addition and checking of terminals

A memory circuit having: a memory array including one or more memory banks; a first processor; and a processor control interface for receiving data processing commands directed to the first processor from a central processor, the processor control interface being adapted to indicate to the central processor when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor.

Memory circuit with integrated processor

An emitter emits a wavelength included in the visible and/or infrared spectrum to illuminate a scene. An observation system is configured to deliver an image representative of the illuminated scene to an observer. The emitter is configured to deliver a light emission by at least one flash with a luminous power greater than a threshold generating dazzling. The observation system presents a first operating condition and a second operating condition of the observed scene to the observer, the second operating condition transmitting less luminous power than the first operating condition. A synchronization circuit is configured to synchronize the emitter and the observation system so that the observer is not dazzled during the emission phase of the emitter.

Growing community of inventors

Lausanne, Switzerland

Fabrice Devaux