Stmicroelectronics S.a.

Infineon Technologies Ag

Vmware, Inc.

Fabrice Devaux

Didier Fuin

Jean-Paul Henriques

Jo&euml;l Curtet

A method for running, on a processor in non-privileged mode, different computer programs P while, in a nominal mode, using privileged instructions including running a hypervisor program in privileged mode of the processor, the hypervisor program providing the computer programs P with services substantially equivalent to those available for running in privileged mode, source codes of the computer programs P being modified beforehand for replacing the privileged instructions with calls for services supplied by the hypervisor program, and the hypervisor program creates at least two privileged submodes organized into a hierarchy within the non-privileged mode and the processor includes only two operating modes.

Methods and systems for CPU virtualization by maintaining a plurality of virtual privilege leves in a non-privileged mode of a processor

The invention concerns a method for read-addressing a site among a plurality of storage units using a coded address derived from an instruction. The method comprises the following steps: a) predicting () the storage unit corresponding to the site to be addressed; b) decoding () the address of the site to be addressed and determining () the storage unit to be addressed; c) managing () a potential read and rewrite conflict assuming that the predicted storage unit is the storage unit to be addressed; d) controlling () the addressing of the predicted storage unit at the end of the managing step (); e) at the end of step b), determining () whether the storage unit to be addressed corresponds to the predicted storage unit; and f) if the storage unit to be addressed does not correspond to the predicted storage unit, managing () a possible read and rewrite conflict in the storage unit to be addressed and addressing the site of the storage unit to be addressed.

Optimised storage addressing method

The present invention relates to a data processing system comprising a processor provided with two memory access units operating in parallel; two separate memories respectively associated with the two access units; and circuitry for, when the address of a datum to be written into a memory is in a predetermined address range, writing the datum into both memories at the same time at the same address.

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Les Marches, France

Fabrice Devaux