Arm Limited

University of Michigan

Fabrice Blanc

Jean-Claude Duby

Mikael Rien

Seshagiri Rao Bogi

Thierry Padilla

David Theodore Blaauw

Parameshwarappa Anand Kumar Savanth

Nidhir Kumar

Vijaya Kumar Vinukonda

Ranabir Dey

Vinay Chenani

Sechang Oh

Mikael Brun

Gurupadayya Shidaganti

Abhinav Kumar

Flora Leymarie

In Hee Lee

Abdellah Bakhali

Gayathri Gandhi

Nicolaas Van Winkelhoff

Matthieu Pauly

Flora Pottier

In a particular implementation, an apparatus to control clamping devices includes a detection circuitry, a clamping device, inverter circuitry, and first and second control circuitry. In response to a first voltage corresponding to a gate terminal of the clamping device, the first control circuitry is configured to generate a second voltage to set the first voltage below a first voltage threshold. Also, in response to the second voltage, the second control circuitry is configured to generate a third voltage to set a voltage of the detection circuitry below a second voltage threshold.

Circuits to control a clamping device

Various implementations described herein are related to a device having switching circuitry that provides a rectified voltage when triggered. The device may include diode circuitry coupled in series with charge storage circuitry. The diode circuitry and the charge storage circuitry may operate to trigger the switching circuitry. The diode circuitry may include one or more diodes, and the charge storage circuitry may include at least one charge storage component.

Rectifier triggering techniques

A level down shifter circuit includes a latch and an assist circuit. The latch is configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain.

Level down shifter

In a particular implementation, an apparatus to control clamping devices includes a first control circuit and a second control circuit. The first control circuit is responsive to a detection signal and generates a first drive signal to control a body diode of a clamping device. The second control circuit is responsive to the detection signal and generates a second drive signal to control the gate terminal of the clamping device.

Devices and methods to control clamping devices

A power supply clamp connectable between power rails of an electronic circuit comprises a switching component which is switchable to provide a connection path between the power rails of the electronic circuit; a first detector configured to detect an electrostatic discharge event having a first characteristic time period and to generate a detector output signal in response to the detection; a series of one or more successive intermediate amplification stages between the first detector and the switching component, the series of amplification stages providing a control signal path for a control signal to control switching of the switching component in response to the detector output signal; and a second detector configured to detect an electrostatic discharge event having a second characteristic time period, shorter than the first characteristic time period, the second detector being provided at a node in the control signal path subsequent to the first detector (for example, at a second or subsequent one of the series of intermediate amplification stages) so that a detection by the second detector causes the control signal to control switching of the switching component.

Power supply clamp

Various implementations described herein are directed to an integrated circuit for electrostatic discharge (ESD) protection. The integrated circuit may include a detection stage having a resistor and a first capacitor cascaded with a second capacitor. The resistor and the first capacitor are arranged to define a triggering node configured to provide a triggering signal. The first capacitor and the second capacitor are arranged to define a reference node configured to provide a reference signal. The integrated circuit may include a first ESD clamping stage having a first transistor configured to provide a supply voltage to a first clamping transistor based on the triggering signal. The integrated circuit may include a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping transistor based on the reference signal.

Electrostatic discharge protection circuitry

A memory device is provided which comprises an array of bitcells and a plurality of wordlines. Each bitcell of the array of bitcells is selectively coupled to a wordline of the plurality of wordlines and access to a selected bitcell of the array of bitcells requires an asserted voltage on a selected wordline with which the selected bitcell is associated. Read assist circuitry is provided, which is configured, when read access to the selected bitcell is carried out, to implement a reduction in the asserted voltage on the selected wordline, and wherein the read assist circuitry is configured to implement the reduction in the asserted voltage by selective connection of the selected wordline to a further wordline of the plurality of wordlines.

Read assist circuitry for a memory device

Circuitry comprises a high voltage rail providing a high voltage level corresponding to a higher voltage domain, an intermediate voltage source, a low voltage rail, and devices that operate in a lower voltage domain. First devices in an upper voltage region are powered between the high voltage rail and an intermediate voltage rail powered by the intermediate source. Second devices in a lower voltage region are powered between the intermediate and low rails. On power up, the intermediate source is powered before the high voltage rail. An isolating circuit connects the intermediate source to a node when the high voltage rail is powered and isolates the node from the intermediate source when the high voltage rail is not powered to impede current flow from the intermediate source to the high voltage rail.

Protecting lower voltage domain devices during operation in a higher voltage domain

An integrated circuit (IC) with electrostatic discharge (ESD) protection includes functional circuitry for performing processing functions required by the IC, and interface circuitry for providing an interface between the functional circuitry and components external to the IC. The IC is formed of a plurality of layers, including component level layers, power grid layers, and intervening layers between the power grid layers and the component level layers providing interconnections between the functional components. The functional circuitry further includes at least one ESD protection circuit constructed so as to reside solely within the component level layers in order to provide ESD protection for an associated one or more of the functional components. Such an approach enables the required ESD protection to be provided locally within the functional circuitry, whilst retaining flexibility with regard to the placement of, and routing between, the various functional components of the functional circuitry.

Integrated circuit and method of providing electrostatic discharge protection within such an integrated circuit

An electrostatic protection apparatus is disclosed that has a voltage level supply configured to supply a voltage level to an electrostatic discharge protection device and the electrostatic discharge protection device that protects a semiconductor electronic device from a rapidly increasing incoming current. The voltage level supply comprises: a voltage divider arranged between high and low voltage rails for supplying an intermediate voltage level to the electrostatic protection device such that a voltage drop across at least some devices within the electrostatic protection device is limited by the intermediate voltage level; a detection device for detecting a signal received from said electrostatic discharge protection device indicating the electrostatic discharge protection device has received the rapidly increasing incoming current; a switching device responsive to the signal to switch the voltage level supplied to the electrostatic discharge protection device from the intermediate voltage level to a voltage level of one of the voltage rails.

Electrostatic discharge protection device having an intermediate voltage supply for limiting voltage stress on components

A cascoded level shifter is subdivided into a first voltage section and a second voltage section, the first voltage section having a lower voltage supply than the second voltage section, and a combined voltage across the first voltage section and the second voltage section corresponding to the high voltage range. The shifter includes an input node receiving an input signal, a cascoded device disposed in one of the first voltage section and the second voltage section, the cascoded device includes a driver switch connected in series with a cascode switch at a midpoint node, the cascode switch switching in dependence on a reference voltage of a reference node and the input signal, and reference voltage perturbation circuitry configured to cause a transient perturbation to the reference voltage in response to a transition of the input signal to cause the cascode switch to switch.

Cascoded level shifter protection

A cascoded level shifter for receiving an input signal in a low voltage range and for generating an output signal in a high voltage range is disclosed. The cascoded level shifter is subdivided into a first voltage section and a second voltage section, the first voltage section having a lower voltage supply than the second voltage section, and a combined voltage across the first voltage section and the second voltage section corresponding to the high voltage range, the cascoded level shifter comprising: an input node configured to receive an input signal; a cascoded device disposed in one of the first voltage section and the second voltage section, the cascoded device comprising a driver switch connected in series with a cascode switch at a midpoint node, the cascode switch switching in dependence on a reference voltage of a reference node and the input signal; and reference voltage perturbation circuitry, configured to cause a transient perturbation to the reference voltage in response to a transition of the input signal to cause the cascode switch to switch.

A power supply cell for distributing power supplied from a first voltage supply to an integrated circuit is disclosed. The power supply cell comprises: a layer comprising conductive material, the conductive material providing a conduction path for current flowing from the first voltage supply to a portion of the integrated circuit to be powered and further providing a protection path for surge current flowing between the first voltage supply and an electrostatic discharge protection device and between the electrostatic discharge protection device and the second voltage supply; the conductive material forming a first conduction path for providing a path for current flowing between the first voltage supply and the portion of the integrated circuit to be powered and for providing a portion of the protection path for surge current flowing between the first voltage supply and the electrostatic discharge protection device and a second conduction path for providing a further portion of the protection path for surge current flowing between the second voltage supply and the electrostatic discharge protection device; wherein the conductive material is arranged such that the first conduction path has a significantly lower resistance than the second conduction path.

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Vinay, France

Fabrice Blanc