Micron Technology Incorporated

Stmicroelectronics S.r.l.

Ovonyx Inc.

Intel Corporation

Other

Ovonyx Memory Technology, LLC

Mircon Technology, Inc.

Fabio Pellizzer

Agostino Pirovano

Innocenzo Tortorelli

Andrea Redaelli

Lorenzo Fratin

Roberto Bez

Ferdinando Bedeschi

Paolo Fantini

Nevil N Gajera

Antonino Rigano

Karthik Sarpatwari

Anna Maria Conti

Augusto Benvenuti

Stephen W Russell

Roberto Somaschini

Russell L Meyer

Cristina Casellato

Carmela Cupeta

Hernan Adolfo Castro

Giorgio Servalli

Hongmei Wang

Kolya Yastrebenetsky

Hari Giduturi

Enrico Varesi

Giulio Casagrande

Roberto Gastaldi

Mattia Robustelli

Michele Magistretti

Andrea Ghetti

Mingdong Cui

Ugo Russo

Davide Fugazza

Marcello Mariani

Yudong Kim

Mario Allegra

Johannes A Kalb

Romina Zonca

Marina Tosi

Osama Khouri

Samuele Sciarrillo

Everardo Torres Flores

Marcello Ravasio

Tony M Lindenberg

Jessica Chen

Pietro Petruzza

Cinzia Perrone

Daniele Ielmini

Loris Vendrame

Alessandro Sebastiani

Riccardo Mottadelli

Tyler A Lowrey

Daniele Vimercati

John Frederic Schreck

Charles C Kuo

Thomas M Graettinger

Stephen J Hudgens

Guy Charles Wicker

Ilya V Karpov

Max F Hineman

Mattia Boniardi

Gianpaolo Spadini

Guido De Sandre

Giulio Albini

Sanjay Rangan

Lingming Yang

Paola Zuliani

George A Gordon

Christina Papagianni

Lei Wei

Jong Won Lee

Srivatsan Venkatesan

Giorgio Pollaccia

Gianfranco Capetti

Eddie T Flores

Nicola Nastasi

Debayan Mahalanabis

Luca Crespi

Derchang Kau

Paolo Giuseppe Cappelletti

Dale Collins

Swapnil Lengade

Roberto Colombo

Andrea Gotti

Claudio Resta

Gerald J Barkley

Davide Mantegazza

Caterina Riva

Lequn Jennifer Liu

Yen Chun Lee

Maria Santina Marangon

Giorgio Bosisio

John Gorman

Federica Zanderigo

Matteo Impala′

Monica Vigilante

Andrea P Marchelli

Lucilla Brattico

Roberta Piva

Laura Aina

Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.

Reading a multi-level memory cell

Memory devices, and associated systems and methods, are disclosed herein. A representative memory device comprises a substrate, an insulative layer over the substrate, and a memory array over the insulative layer. The memory device further comprises a fuse array positioned in the insulative layer and configured as a non-volatile memory that can store trimming and/or other factors. The fuse array can comprise a plurality of transistors configured as fuses and each including a source, a drain, and a gate. The transistors in a first subset of the transistors have a first resistance across one of the source, the drain, and the gate that represents a first logic state, and the transistors in a second subset of the transistors can have a second resistance across the one of the source, the drain, and the gate that is greater than the first resistance and that represents a second logic state.

Memory devices having one-time-programmable fuses and/or antifuses formed from thin-film transistors

Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.

Varying-polarity read operations for polarity-written memory cells

Systems, methods, and apparatuses are provided for unipolar programming of memory cells in a semiconductor device. A memory has a plurality of self-selecting memory cells and circuitry configured to program a self-selecting memory cell of the plurality of self-selecting memory cells to a first data state or a second data state by applying a current pulse to the self-selecting memory cell. The current is a set pulse or a reset pulse. The set pulse and the reset pulse have a same polarity.

Unipolar programming of memory cells

Methods, systems, and devices for a vertical memory architecture are described. A memory device may include memory cells arranged in a three-dimensional vertical memory architecture. Each memory cell may include a storage element (e.g., a chalcogenide material), where a logic state may be programmed at the storage element based on a polarity of an applied voltage that exceeds a threshold voltage. The storage element may be coupled with a selection element and a conductive line. The selection element may be coupled with a bit line decoder and a word line decoder via vertical pillars. The selection element may selectively couple the storage element with the bit line decoder. In some examples, an activation voltage for the selection element may be less than a threshold voltage of the storage element.

Vertical memory architecture

A semiconductor device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction, memory cells disposed between the first conductive lines and the second conductive lines, each memory cell disposed at an intersection of a first conductive line and a second conductive line, and a passive material between the memory cells and at least one of the first conductive lines and the second conductive lines. Related semiconductor devices and electronic devices are disclosed.

Devices including a passive material between memory cells and conductive access lines, and related electronic devices

Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.

Cross-point pillar architecture for memory arrays

Methods, systems, and devices for decoder architectures for three-dimensional memory devices are described. In some cases, a decoder for a memory device may include two portions. A first portion of the decoder may be manufactured on top of the memory array, and may include a pillar decoding portion to selectively bias a first array of decoding elements coupled with conductive pillars of the memory array and a word line decoding portion to selectively bias a second array of decoding elements coupled with word lines of the memory array. A second portion of the decoder may be implemented in a separate semiconductor device which may include a set of logic circuits configured to drive signal to a set of contacts bonded to contacts of the first portion to drive the digit lines, voltage sources, and gate lines.

Decoder architectures for three-dimensional memory devices

Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Spike current suppression is implemented using a folded access line structure. Each access line includes integrated top and bottom insulating layers that restrict current flow to the memory cells through a narrower middle portion of the access line. For near memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the meandering, folded circuit path that flows through the middle portion. Spike discharge that occurs when the memory cell is selected is reduced by this higher resistance path.

Folded access line for memory cell access in a memory device

Methods for, apparatuses with and vertical 3D memory devices are described. A vertical 3D memory device may comprise: a plurality of contacts associated with a plurality of digit lines and extending through a substrate; a plurality of word line plates separated from one another by respective dielectric layers and including a first plurality of word line plates and a second plurality of word line plates; a first dielectric material positioned between the first plurality and the second plurality of word line plates, the first dielectric material extending in a serpentine shape over the substrate; a conformal material positioned between the first dielectric material and the first and second plurality of word line plates, respectively; a plurality of spacers; a plurality of pillars coupled with the plurality of contacts; and a plurality of storage elements each comprising chalcogenide material positioned in a recess.

Memory device and method for manufacturing the same

Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.

Techniques for forming self-aligned memory structures

Methods, systems, and devices for techniques for operating a vertical memory architecture are described. A memory device may include memory cells arranged in a three-dimensional vertical memory architecture. Each memory cell may include a storage element (e.g., a chalcogenide material), where a logic state may be programmed at the storage element based on a polarity of an applied voltage that exceeds a threshold voltage. The storage element may be coupled with a selection element and a conductive line. The selection element may be coupled with a bit line decoder and a word line decoder via vertical pillars. The selection element may selectively couple the storage element with the bit line decoder. In some examples, an activation voltage for the selection element may be less than a threshold voltage of the storage element.

Operating a chalcogenide memory with vertical word and vertical word switching elements

Methods, systems, and devices for split pillar architectures for memory devices are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars may be divided to form first and second pillars.

Split pillar architectures for memory devices

Methods, systems, and devices for memory device with a split pillar architecture are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars and cell material may be divided to form a first and second storage components and first and second pillars.

Memory device with a split pillar architecture

Methods, systems, and devices for decoding for a memory device are described. A decoder may include a first vertical n-type transistor and a second vertical n-type transistor that extends in a third direction relative to a die of a memory array. The first vertical n-type transistor may be configured to selectively couple an access line with a source node and the second n-type transistor may be configured to selectively couple the access line with a ground node. To activate the access line coupled with the first and second vertical n-type transistors, the first vertical n-type transistor may be activated, the second vertical n-type transistor may be deactivated, and the source node coupled with the first vertical n-type transistor may have a voltage applied that differs from a ground voltage.

Decoding for a memory device

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Boise, ID, United States of America

Fabio Pellizzer