Infineon Technologies Ag

Infineon Technologies Austria Ag

Fabio Padovan

Dmytro Cherniak

Giovanni Boi

Luigi Grimaldi

Matteo Bassi

Vadim Issakov

Karl Norling

David Seebacher

Thomas Bauernfeind

Simone Fabbro

Philipp Franz Freidl

Mattias Welponer

Saleh Karman

Mateo Bassi

Natasa Pojak

Andrew Wightwick

Fabio Versolatto

A calibration circuit may include a calibration signal generator configured to receive an oscillator signal provided by an oscillator and generate a calibration signal based on the oscillator signal. The calibration signal may be generated to have a predetermined amplitude. The calibration circuit may include a calibration peak detector configured to detect a peak amplitude of the calibration signal. The calibration circuit may include a logic circuit configured to calibrate a peak detector connected to the oscillator based at least in part on the peak amplitude of the calibration signal.

Peak detector calibration

A device includes: first and second electronic sides; an isolation barrier galvanically isolating the electronic sides from one another and including a signal coupler configured to enable signaling between the electronic sides over the isolation barrier via electromagnetic coupling; and transceiver circuitry included in both electronic sides and configured to implement, based on a frequency response profile of the isolation barrier, full-duplex communication between the electronic sides using the same signal coupler. According to another embodiment of a device, the device includes: electronic circuitry; an isolation barrier galvanically isolating the electronic circuitry and including a signal coupler configured to enable signaling over the isolation barrier via electromagnetic coupling; and transceiver circuitry configured to implement, based on a frequency response profile of the isolation barrier, full-duplex communication between the electronic circuitry of the device and electronic circuitry of another device using the same signal coupler.

Devices, systems and methods for multiple channel communication across an isolation barrier

A digital phase-locked loop (DPLL) may include a delta-sigma modulator (DSM). The DSM may include a delay component configured to perform noise shaping of a quantization error introduced by the DSM. The DSM may include a noise transfer function (NTF) component configured to perform filtering of the quantization error introduced by the DSM. The DSM may include an adjustment transfer function (ATF) component configured to cause the filtering of the quantization error to be applied on top of the noise shaping such that an impact of the NTF component on the noise shaping is reduced.

Delta-sigma modulator with modified quantization error shaping

A digital phase-locked loop (DPLL) circuit includes: a first time-to-digital converter (TDC) and a first digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), where the first TDC is configured to, during an acquisition mode, generate a phase error by: receiving a reference clock signal from the reference clock source; receiving a clock signal that is based on an output of the DCO divided by a dividing factor, computing a phase error using the reference clock signal and the clock signal; detecting cycle slipping in the computed phase error; and in response to detecting the cycle slipping, modifying the computed phase error to reduce the impact of cycle slipping on the DPLL circuit; and a first frequency divider circuit configured to generate the clock signal by dividing the output of the DCO by the dividing factor.

Digital coarse locking in digital phase-locked loops

In accordance with an embodiment, a method for operating a millimeter-wave power amplifier including an input transistor having an output node coupled to a load path of a cascode transistor includes: receiving a millimeter-wave transmit signal at a control node of the input transistor; amplifying the millimeter-wave transmit signal to form an output signal; providing the output signal to a load coupled to an output node of the cascode transistor; and adjusting a first DC bias current of the input transistor to form a substantially constant second DC bias current of the cascode transistor.

Millimeter-wave power amplifier

An oscillator includes: a first inductor; and a programmable capacitor bank coupled between a first terminal of the first inductor and a second terminal of the first inductor, where the programmable capacitor bank includes a plurality of cells concatenated together, where each cell of the plurality of cells includes a first node, a second node, a third node, a second inductor, and a programmable capacitor, where the second inductor is coupled between the first node and the third node, and the programmable capacitor is coupled between the third node and the second node, where a first inductance of the first inductor is larger than a sum of the inductances of the second inductors of the programmable capacitor bank.

Oscillator with inductor and programmable capacitor bank

A method of operating a phase-locked loop (PLL) having a dynamic element matching (DEM)-driven digitally controlled oscillator (DCO) includes calibrating the PLL, where calibrating the PLL includes opening a loop of the PLL and performing linearity measurements of the DEM-driven DCO when the loop of the PLL is open and when dynamic matching of the DEM-driven DCO is activated, where performing the linearity measurements includes: applying test control words to the DEM-driven DCO to obtain frequencies in a first range of frequencies; and measuring output frequencies of the DEM-driven DCO corresponding to the test control words. Calibrating the PLL further includes calculating calibration information based on the test control words and the measured output frequencies.

Digital phase-locked loop with a dynamic element matching circuit and a digitally controlled oscillator

A calibration circuit for calibrating a peak detector configured to detect a signal peak amplitude of an oscillator, including: a calibration oscillator configured to be supplied by at least two different supply voltages to generate respective calibration signals; a calibration peak detector configured to detect a calibration signal peak amplitude of each of the calibration signals; and a logic circuit configured to calibrate the peak detector based on the detected calibration signal peak amplitudes.

A frequency multiplier comprises a phase generator configured to receive an oscillation signal and to provide at phase generator outputs versions of the oscillation signal, which are phase-shifted with respect to each other. An injection-locked ring oscillator comprises a plurality of stages, wherein each of the phase generator outputs is coupled to a different stage of the plurality of stages for multi-point injection. A combiner combines output signals of the plurality of stages of the injection-locked ring oscillator into a signal having a frequency which is a multiple of a frequency of the oscillation signal.

Frequency multiplier and method for frequency multiplying

A circuit for calibrating an injection locked oscillator is provided. The injection locked oscillator includes an injection locking input, an LC tank and an oscillator output to output an oscillator output signal. The circuit is configured to adjust a capacitance of the LC tank to different values, detect an amplitude of the oscillator output signal for each value of the different values of the capacitance while an input signal having a target frequency is applied to the injection locking input, determine a maximum amplitude of the detected amplitudes, and select a value for operating the injection locked oscillator based on the determined maximum amplitude.

Calibrating an injection locked oscillator

An integrated circuit is described herein. In accordance with one embodiment, the circuit includes a voltage controlled oscillator (VCO) that is configured to receive a tuning voltage at a tuning input and to provide an RF oscillator signal at an oscillator output. The circuit further includes a first and a second switchable resistor network. The first switchable resistor network includes at least a first resistor and at least a first switch and is connected between the tuning input of the VCO and a first node, which operably provides a first voltage. The second switchable resistor network includes at least a second resistor and at least a second switch and is connected between the tuning input of the VCO and a second node, which operably provides a second voltage. Furthermore, the circuit includes a control circuit that is configured to activate, dependent on a control signal, either the first switchable resistor network, the second switchable resistor network or both, the first and the second resistor networks.

Testing properties of a voltage-controlled oscillator

In accordance with an embodiment, a method of operating a voltage controlled oscillator (VCO) that having a VCO core coupled to a filtered current source includes setting an oscillation frequency of the VCO core based on a tuning signal received at a tuning signal input; and setting a resonant frequency of the filtered current source based on the received tuning signal using a tuning circuit having an input directly connected to the tuning signal input.

System and method for a VCO

In accordance with an embodiment, a method of operating a voltage controlled oscillator (VCO) includes generating a first oscillating signal in a first VCO core and generating a second oscillating signal in a second VCO core, such that the first oscillating signal and the second oscillating signal have a same frequency and a fixed phase offset. The VCO includes the first VCO core and the second VCO core, and each VCO core includes a pair of transistors. The VCO also includes a transformer having a first winding coupled between control nodes of the pair of transistors of the first VCO core and a second winding coupled between control nodes of the pair of transistors of the second VCO core.

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Villach, Austria

Fabio Padovan