Freescale Semiconductor,inc.

Fabio De Lacerda

Alfredo Olmos

Andre Luis Vilas Boas

Fabio Duarte De Martin

Edgar Mauricio Camacho Galeano

Jefferson Daniel De Barros Soldera

A low voltage detector () includes a power supply voltage monitor circuit () that produces a voltage Vrelated to a first a power supply voltage, and a voltage generator (), which includes a plurality of self-cascode MOSFET (SCM) structures (-) in a cascade configuration, that generates a reference voltage V. A voltage comparator () outputs an output signal in response to a differential between Vand V, wherein Vand Vhave proportional to absolute temperature behavior (PTAT) over temperature with respect to a second power supply voltage. The output signal changes state when the first power supply voltage equals a trip point of the comparator. Each SCM structure is sized to provide a rate of change with temperature of the PTAT behavior of Vthat matches a rate of change with temperature of the PTAT behavior of V.

Low voltage detector

A process of forming an electronic device can include forming a capacitor dielectric layer over a base region, wherein the base region includes a base semiconductor material, forming a gate dielectric layer over a substrate, forming a capacitor electrode over the capacitor dielectric layer, forming a gate electrode over the gate dielectric layer, and forming an input terminal and an output terminal to the capacitor electrode. The input terminal and the output terminal can be spaced apart from each other and are connected to different components within the electronic device. A filter can include the base region, the capacitor dielectric layer, and the capacitor electrode. A transistor structure can include the gate dielectric layer and the gate electrode. An electronic device can include a low-pass filter and a transistor structure, such as an n-channel transistor or a p-channel transistor.

Process of forming an electronic device including a resistor-capacitor filter

A low voltage detector () includes a voltage and current reference circuit (); a power supply voltage monitor circuit (), coupled to the voltage and current reference circuit and to a power supply; and a voltage comparator (), coupled to the voltage and current reference circuit and to the power supply voltage monitor circuit. The voltage and current reference circuit includes a self-cascode MOSFET structure (SCM) () that produces a reference voltage. The power supply voltage monitoring circuit includes another SCM () that produces a monitor voltage, related to the power supply voltage. The reference voltage and the monitor voltage have a same behavior with changes in temperature, thereby allowing the trip point of the low voltage detector to minimally vary with temperature. The low voltage detector is disposed on an integrated circuit (), and the transistors of the low voltage detector consist of only CMOS transistors.

A switched-capacitor amplifier circuit (and) with rail-to-rail capability without requiring a rail-to-rail operational amplifier includes a switched-capacitor amplifier (and) and an input network () coupled to the switched-capacitor amplifier. The switched-capacitor amplifier includes a non-rail-to-rail operational amplifier (and). The input network prevents the non-rail-to-rail operational amplifier from receiving an input differential signal that has a common-mode voltage at or near rails of the non-rail-to-rail operational amplifier. Voltages at input terminals of the operational amplifier remain near analog ground, which is an arbitrary voltage level between the rails, during both phases of switching in the switched-capacitor amplifier. In one embodiment, the switched-capacitor amplifier uses a correlated double sampling technique.

Switched-capacitor amplifier circuit

Methods and corresponding systems for reading a memory cell include a first current sourced from a first current source into a summing node, wherein the first current source is coupled to a first reference. A second current is sourced from a second current source into the summing node, wherein the second current source is coupled to the first reference through a programmable fuse. A third current is sunk from the summing node with a current sink, wherein the current sink is coupled to a second reference, and wherein a third current limit is greater than a first current limit and less than the sum of the first current limit and the second current limit. A voltage at the summing node is output in response to the first current, the second current, and the third current. The first and second current sources, and the current sink can be current mirrors.

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Niteroi, Brazil

Fabio De Lacerda