Intel Corporation

Fabio Checconi

Fabrizio Petrini

Robert Pawlowski

A memory architecture may provide support for any number of direct memory access (DMA) operations at least partially independent of the CPU coupled to the memory. DMA operations may involve data movement between two or more memory locations and may involve minor computations. At least some DMA operations may include any number of atomic functions, and at least some of the atomic functions may include a corresponding return value. A system includes a first direct memory access (DMA) engine to request a DMA operation. The DMA operation includes an atomic operation. The system also includes a second DMA engine to receive a return value associated with the atomic operation and store the return value at a source memory.

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Santa Clara, CA, United States of America

Fabio Checconi