International Business Machines Corporation

Columbia University

Ulvac, Inc.

Fabio Carta

Chung H Lam

Matthew Joseph BrightSky

Bahman Hekmatshoartabari

Robert L Bruce

Wanki Kim

Daniel C Edelstein

Tak H Ning

Stephen McConnell Gates

Takeshi Masuda

Ioannis Kymissis

Devendra K Sadana

Ning Li

Tze-Chiang Chen

Hiroyuki Miyazoe

SangBum Kim

Zhang Jia

Koukou Suu

Kumar R Virwani

Asit Kumar Ray

Nadia Pervez

Norma Edith Sosa

Jun Shimada

Gloria W Fraczak

Gloria W Y Fraczak

Shyuan Yang

Gloria Wing Yun Fraczak

Maxence Bouvier

Matthew Brightsky

Matthew Joseph Brightsky

A cross-point memory semiconductor structure and a method of creating the same are provided. There is a first electrode layer on top of the substrate. A conductive oxide diffusion barrier layer is on top of the first electrode. A polycrystalline silicon diode is on top of the conductive oxide diffusion barrier. A phase change material (PCM) layer is on top of the polycrystalline silicon diode. A second electrode is on top of the PCM layer.

Conductive oxide diffusion barrier for laser crystallization

A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.

Integration of selector on confined phase change memory

A method of manufacturing a vertical metal-semiconductor field-effect transistor (MESFET) device is provided. The method includes forming a first oxide layer, forming a first electrode in the oxide layer, forming a crystallized silicon layer on the first electrode, forming a second electrode on the first oxide layer and on sidewalls of the crystalized silicon layer, forming a second oxide layer on upper surfaces of the second electrode. The method also includes forming a third electrode on an upper surface of the crystallized silicon layer.

3D stackable bidirectional access device for memory array

According to one embodiment, a method, computer system, and computer program product for increasing linearity of a weight update of a phase change memory (PCM) cell is provided. The present invention may include applying a RESET pulse to amorphize the phase change material of the PCM cell; responsive to applying the RESET pulse, applying an incubation pulse to the PCM cell; and applying a plurality of partial SET pulses to incrementally increase the conductance of the PCM cell.

Pulsing synaptic devices based on phase-change memory to increase the linearity in weight update

A method of fabricating an access device in a crosspoint memory array structure during BEOL processing includes: forming at least a first doped semiconductor layer on an upper surface of a first conductive layer, the first doped semiconductor layer being in electrical connection with the first conductive layer; exposing at least a portion of the first doped semiconductor layer to a directed energy source to cause localized annealing in the first doped semiconductor layer to activate a dopant of a first conductivity type in the first doped semiconductor layer, thereby converting at least a portion of the first doped semiconductor layer into a polycrystalline layer; forming a second conductive layer over a least a portion of the first doped semiconductor layer; and etching the first doped semiconductor layer and the first and second conductive layers to form an access device that is self-aligned with the first and second conductive layers.

Crosspoint phase change memory with crystallized silicon diode access device

A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction, depositing a phase change material over the p-n junction, and forming a second electrode over the phase change material.

Crystallized silicon vertical diode on BEOL for access device for confined PCM arrays

A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.

Access device and phase change memory combination structure in backend of line (BEOL)

A phase change memory array and method for fabricating the same. The phase change memory array includes a plurality of bottom electrodes, top electrodes, and memory pillars. Each of the memory pillars includes phase change material surrounded by a dielectric casing. The phase change material is positioned between, and in series circuit with, a respective bottom electrode from the bottom electrodes and a respective top electrode from the top electrodes. A continuous layer of selector material is positioned between the memory pillars and the plurality of bottom electrodes. The selector material is configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold.

Integration of confined phase change memory with threshold switching material

A method for deactivating memory cells affected by the presence of grain boundaries in polycrystalline selection devices includes crystallizing a semiconductor layer in a diode stack to form a polycrystalline layer for selection diodes formed in a crossbar array. To achieve a crystalline state in phase change memory elements coupled to corresponding selection diodes perform an anneal. Memory cells having shunted selection diodes due to grain boundaries are identified by scanning the array using sense voltages. A second voltage larger than the sense voltages is applied to the phase change memory elements gated by the shunted selection diodes such that the phase change memory elements gated by the shunted diodes achieve a permanently high resistive state.

Phase change memory array with integrated polycrystalline diodes

A method of forming a phase change material is provided in which the crystalline state resistance of the material can be controlled through controlling the flow ratio of NH/Ar. The method may include providing a flow modulated chemical vapor deposition apparatus. The method may further include flowing gas precursors into the flow modulated chemical vapor deposition apparatus to provide the base material components of the phase change material. The method further includes flowing a co-reactant precursor and an inert gas into the flow modulated chemical vapor deposition, wherein adjusting ratio of the co-reactant precursor to the inert gas adjusts the crystalline state resistance of the phase change material.

Composition control of chemical vapor deposition nitrogen doped germanium antimony tellurium

Method(s) and apparatuses for forming a phase change memory. A method includes: forming a crystalline phase-change layer at a first position in along a surface of a first semiconductor layer, and forming an amorphous phase-change layer at a second position along the surface of a second semiconductor layer, wherein the crystalline phase-change layer and the amorphous phase-change layer are in contact.

Method for manufacturing phase change memory

A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, and forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction. The method further includes depositing a second electrode between a set of spacers and in direct contact with the p-n-junction, depositing a phase change material over the p-n junction and in direct contact with the second electrode, and forming a third electrode over a portion of the phase change material.

A method of forming a phase change material memory array is provided. The method includes forming a lower metallization layer on a substrate, and forming a plurality of upright slabs, where each of the slabs includes a lower buffer segment on the lower metallization layer, a phase change material segment on the lower buffer segment, an upper buffer segment on the phase change material segment, and an upper conductive segment on the upper buffer segment. The method further includes forming a resistive liner on the plurality of upright slabs, and forming a sidewall spacer layer on the resistive liner. The method further includes removing portions of the sidewall spacer layer and the resistive liner on the substrate and the upper conductive segment, wherein another portion of the resistive liner remains on the phase change material segment.

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Pleasantville, NY, United States of America

Fabio Carta