Apple Inc.

Fabien S Faure

Robert E Jeter

Rakesh L Notani

Sukalpa Biswas

Kai Lun Hsiung

Venkata Ramana Malladi

Arnaud J Forestier

Manu Gulati

Brijesh Tripathi

Neeraj Parik

Kiran Kattel

Vikram Mehta

Allen Kim

Shiva Kumar

Chaitanya Polapragada

Pradeep R Trivedi

Mansour Keramat

Parin Patel

Gregory S Mathews

Liang Deng

Shy Hamami

Tristan R Hudson

Huaimin Li

Yaron Cohen

Enming Zheng

Si Chen

A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

Built-in self-test for die-to-die physical interfaces

A voltage monitoring circuit is disclosed. An apparatus includes a first physical interface circuit and a real-time oscilloscope circuit configured to monitor a first voltage provided to the first physical interface circuit. The real-time oscilloscope is configured to receive an indication that an error was detected in data transmitted from the first physical interface to a second physical interface circuit. The real-time oscilloscope is further configured to provide for debug, to a host computer external to the first interface, information indicating a state of the first voltage at a time at which the error was detected.

Voltage monitoring circuit for interface

An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.

Reference voltage calibration using a qualified weighted average

A method and apparatus for predicting a reference voltage in a memory subsystem is disclosed. A memory subsystem includes a memory controller coupled to a memory. The memory controller includes a lookup table having a number of different reference voltage values each corresponding to one of a number of different performance states. The memory controller further includes calibration circuitry configured to determine reference voltages for operation in various performance states. Responsive to returning to a performance state after operating in another, the calibration circuitry may restore the reference voltage to its most recently used value, and also obtain a predicted reference voltage. Calibrations may be performed at both the restored reference voltage and the predicted reference voltage obtained from the lookup table. The subsequent operating reference voltage may then be selected based on which of the two calibrations resulted in the largest data eye width.

Reference voltage prediction in memory subsystem

An apparatus includes an oscillator circuit, a counter circuit, and a control circuit. The oscillator circuit may receive an input clock signal and an inverse input clock signal, and, for a first time period, may generate an oscillator output signal with a frequency based on a duty cycle of the input clock signal. For a second time period, the oscillator circuit may generate the oscillator output signal with a frequency based on a duty cycle of the inverse input clock signal. The counter circuit may count oscillations of the oscillator output signal over the first time period and over the second time period. The control circuit may determine, based on the oscillations counted by the counter circuit during the first time period and the second time period, a duty cycle value indicative of the duty cycle of the input clock signal.

Digital on-chip duty cycle monitoring device

A method and apparatus for performing a background calibration in a memory subsystem is disclosed. A memory subsystem includes a memory controller coupled to a memory. The memory controller is coupled to receive data during reads from the memory on a functional data path and a duplicate data path. The memory controller further includes calibration circuitry. During reads of data conducted during normal operation, the calibration circuit calibrates a first delay locked loop (DLL) in the duplicate data path. A second DLL, in the functional data path, may be adjusted based on the calibrations conducted in the duplicate data path.

Method and apparatus for background memory subsystem calibration

Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half. If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.

Systems and methods for dynamically switching memory performance states

A method and apparatus for adaptive calibration scheduling is disclosed. A calibration circuit may perform calibrations of a delay applied to a data strobe conveyed from a memory controller to the memory, and may also calibrate a reference voltage. After calibrating the data strobe delay, a current width of an eye opening and a current score are determined. If the eye opening is not less than a minimum threshold and the current score is within a specified range of a reference score, the reference voltage calibration, if conditionally scheduled, is inhibited. The results of the calibration may be recorded in a history table. A timer may advance a pointer provided to a sequence table at a rate determined by information stored in the history table. Information stored in an entry of the sequence table may indicate which calibration procedures are to be performed during the next calibration cycle.

Adaptive calibration scheduling for a memory subsystem based on calibrations of delay applied to data strobe and calibration of reference voltage

A method and apparatus for using neighboring sampling points in a memory subsystem calibration is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller coupled thereto. A calibration unit in the memory controller is configured to perform calibrations of a data strobe signal and a reference voltage to determine eye openings for signals conveyed between the memory and the memory controller. Performing the calibration includes determining a number of different calibration points and computing initial scores for each of the calibration points. The method further includes calculating adjusted scores for each calibration point. For a given calibration point, the adjusted score includes weighted values of one or more calibration points that are adjacent thereto. The method further includes selecting a calibration point having the highest adjusted score as the calibrated value.

Systems and methods using neighboring sample points in memory subsystem calibration

In an embodiment, a system includes a power management unit (PMU), a non-volatile memory, a volatile memory, and a processor. The PMU may be configured to generate a power supply voltage, change a state of a status signal responsive to an event, and reduce a voltage level of the power supply voltage responsive to a predetermined period of time elapsing from detecting the event. The system may be configured to transition from a first to a second operating mode responsive to the change of the state of the status signal, and cancel pending commands to the non-volatile memory responsive to the transition to the second operating mode. The non-volatile memory may be configured to complete active commands prior the predetermined period of time elapsing.

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Santa Clara, CA, United States of America

Fabien S Faure