Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Commissariat a L'energie Atomique

Stmicroelectronics (canada), Inc.

Commissariat a L'energie

Fabien Clermidy

Didier Lattard

Thierry Collette

Romain Lemaire

Pascal Vivet

Christian Bernard

Sébastien Thuries

Pascal Benoit

Marc Belleville

Didier Varreau

Edith Beigne

Olivier Billoint

Diego Puschini Pascual

Charles Pilkington

Michel Langevin

Santhosh Onkaraiah

Imen Mansouri

Hughes Metras

Mickaël Guibert

Thiago Raupp Da Rosa

Hossam Sarhan

A tier of a 3D circuit comprising: one or more macro circuits, each macro circuit comprising a plurality of macro cells arranged in an array, the macro cells being separated from each other by spaces; and interconnection vias positioned in the spaces between the macro cells.

Integrated circuit comprising macros and method of fabricating the same

An electronic circuit including a bipolar switching memory device including first and second electrodes at terminals of which a programming voltage can be applied, the circuit including: a first mechanism applying, to the first electrode, a data signal having, during a time period d, a constant state 0 or 1; a second mechanism applying, to the second electrode, a control signal that alternates, during time period d, between state 1 and state 0, the control signal being same regardless of the state in which the memory device is programmed; a selection device allowing a current to flow into the memory device during a programming time included in time period d; and a change of state of the control signal taking place during the programming time.

Method for programming a bipolar resistive switching memory device

A system including at least one computation node including a memory, a processor reading/writing data in a work area of the memory and a DMA controller including a receiver receiving data from outside and writing it in a sharing area of the memory or a transmitter reading data in said sharing area and transmitting it outside. A write and read request mechanism is provided in order to cause, upon request of the processor, a data transfer, by the DMA controller, between the sharing area and the work area. The DMA controller includes an additional transmitting/receiving device designed for exchanging data between outside and the work area, without passing through the sharing area.

System-on-chip and method for exchanging data between computation nodes of such a system-on-chip

The invention concerns a 3D circuit design method implemented by a processing device involving partitioning a 2D circuit representation into two or more tiers, the 2D circuit representation defining circuit elements interconnected by interconnecting wire each weighted based on at least one of: its length; its propagation delay; and its priority level, the 2D circuit representation initially forming a first tier, the partitioning involving: a) selecting a first highest ranking wire, interconnecting at least first and second circuit elements in the first tier; b) moving one of the first and second circuit elements connected by the selected wire to a further tier of the 3D circuit representation and replacing the interconnecting wire with a connecting via between the first and further tiers; and c) repeating a) and b) for one or more further interconnecting wires of the first tier.

3D circuit design method

A network interface for a first network on chip resource capable of interfacing a data processing unit in the first resource with the network, the network interface including an output communication controller including a mechanism detecting an indicator marking an end of communication between the first resource and at least one second resource with which a communication link is set up, and a mechanism outputting a signal indicating closure of the link to be sent to the second resource, after detection of an end of communication indicator.

Network interface for a SoC comprising an improved communication controller

A method for optimizing operation which is applicable to a multiprocessor integrated circuit chip. Each processor runs with a variable parameter, for example its clock frequency, and the optimization includes determination, in real time, of a characteristic data value associated with the processor (temperature, consumption, latency), transfer of the characteristic data to the other processors, calculation by each processor of various values of an optimization function depending on the characteristic data value of the block, on the characteristic data values of the other blocks, and on the variable parameter, the function being calculated for the current value of this parameter and for other possible values, selection, from among the various parameter values, of that which yields the best value for the optimization function, and application of this variable parameter to the processor for the remainder of the execution of the task.

Method for optimizing the operation of a multiprocessor integrated circuit, and corresponding integrated circuit

A system for designing digital circuitry comprising: a digital circuit simulator based on a file containing a functional description of this digital circuit; means for estimating an output variable from the digital circuit when executing a test bench supplied to the simulator; event counters, the events being detected using control signals provided by the simulator when executing the test bench. Said system further comprises means for selecting a portion of the event counters by iteratively optimizing a model for calculating the output variable of the digital circuit using output data from the event counters and means for registering the selected portion of event counters and the optimized calculation model.

System and method for designing digital circuitry with an activity sensor

This invention relates to a system on chip for data flow type application. The system comprises a network on chip, a central controller and processing units connected to said network via associated network interfaces. A processing unit and/or its associated network interface can be configured on command from the central controller or on a command incorporated in a data packet to be processed. The network interface comprises a client module that can request a configuration server to transmit the parameters of a configuration that is unavailable in the interface. The invention also relates to a mobile terminal/ a base station comprising a base band modem implemented by such a system on chip.

System on chip with interface and processing unit configurations provided by a configuration server

This invention relates to the domain of Networks on Chips (NoC) and relates to a method of transferring data in a network on chip, particularly using an asynchronous 'send/accept' type protocol. The invention also relates to a network on chip used to implement this method.

Globally asynchronous communication architecture for system on chip

A data processing method in a network on chip formed of a plurality of processors configured to communicate between one another, and at least one network controller configured to initialize communications in the network, the method including: receiving and storing in a memory by a first processor, one or more credit management configuration programs received from the network controller, and establishing a first communication between at least said first processor and at least one second processor.

NoC semi-automatic communication architecture for 'data flows' applications

The invention relates to a component with a large grain dynamically reconfigurable architecture for processing of data by processing units organized in rows and connected to each other through interconnections so as to enable processing in pipeline or parallel mode or in dependent rows mode. All data types may be processed and the component may process several applications at the same time. The choice of the grain, control at several levels with limited control interconnection resources and the data distribution circuit enable local or general reconfiguration of the component in one clock cycle.

Component with a dynamically reconfigurable architecture

Reconfiguration method applicable to an array of identical functional elements

This invention relates to a network of parallel elementary processors, tolerant to the faults of these processors including said elementary processors, spare elementary processors, elements interconnecting these processors and a control unit, and alternately a series of interconnecting element lines and processor lines, each processor being surrounded by four interconnecting elements, the processor lines being elementary processor lines, the last processor line being a line of spare processors, the edge elements of the network being interconnecting elements, wherein the control unit, connected to processors and interconnecting elements, sends instructions to the processors, controls the interconnecting elements, and checks the integrity of these processors.

Growing community of inventors

Saint-Egreve, France

Fabien Clermidy