Lattice Semiconductor Corporation

Advanced Micro Devices Corporation

Vantis Corporation

Fabiano Fontana

Om P Agrawal

Howard H Tang

Jack Tim Wong

Henry Law

David Lee Rutledge

Bradley A Sharpe-Geisler

Sunil D Mehta

Satwant Singh

Brad Sharpe-Geisler

David W Chang

Sam Tsai

Gilles Bosco

Timothy Scott Swensen

Martha Chan

Susan Nguyen

Hok Wong

Mathew A Rybicki

James A Watson

Zheng Chen

Loren McLaury

Robert Gary Pollachek

Rohith Sood

Ammisetti V Prasad

Benjamin Lau

Steve Choi

Jenny Chui

In one embodiment, a memory includes a plurality of bit lines and a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation. The write driver is coupled to an internal node. A first stage clamping circuit is operable to clamp the internal node to a clamping voltage if the write operation is not enabled and is further operable to unclamp the internal node during the write operation. The memory further includes a multiplexer for selectively coupling the driven bit line to the internal node. A second stage clamping circuit is operable to clamp the plurality of bit lines to a clamping voltage if the write operation is not enabled and is further operable to unclamp the driven bit line during the write operation.

Dual-port SRAM with bit line clamping

In one embodiment, a voltage discharge (VD) system has a slow VD subsystem that provides two concurrent discharge current paths to at least begin to discharge both positive and negative voltages: a first path from the positive-voltage node to ground and a second path from the positive-voltage node to the negative-voltage node. In addition to this relatively slow VD subsystem, the VD system can also have a conventional fast VD subsystem that is turned on after the slow VD subsystem has reduced the positive and negative voltages to some degree (e.g., half of each charge removed). Such a VD system can eliminate dangerous overshoot conditions, even when control-signal skew is present.

Voltage discharge circuit having divided discharge current

In one embodiment, a memory is provided that includes: a write driver for selectively driving a driven pair of bit lines selected from a plurality of bit line pairs during a write operation; a first stage clamping circuit operable to clamp a pair of internal nodes to a clamping voltage, wherein the first stage clamping circuit is further operable to unclamp the pair of internal nodes during the write operation; a bit line multiplexer for selectively coupling the driven bit line pair to the pair of internal nodes; and a second stage clamping circuit operable to clamp the plurality of bit line pairs to the clamping voltage, wherein the second stage clamping circuit is further operable to unclamp the driven bit line pair during the write operation.

Techniques are provided which may be used to reduce power consumed by memory circuits. In one example, a memory circuit includes a static random access memory (SRAM) cell. A pair of bitlines are connected to the SRAM cell. A precharge circuit is connected to the bitlines. The precharge circuit is adapted to precharge the bitlines immediately prior to read and write operations performed on the SRAM cell and float relative to the bitlines at other times.

Bitline floating circuit for memory power reduction

In one embodiment, a programmable logic device includes a plurality of logic blocks; a plurality of input/output blocks; volatile configuration memory adapted to store configuration data for configuration of the logic blocks and input/output blocks; embedded block RAM adapted to store user data; flash memory having at least a first partition and a second partition; and a data port adapted to provide external device access to the first partition of the non-volatile memory. The flash memory is adapted to store within the first partition user data from the data port and is further adapted to store within the second partition user data from the embedded block RAM.

Flexible memory architectures for programmable logic devices

In one embodiment, an integrated circuit (IC) such as a programmable logic device includes a plurality of IC input terminals and an input buffer having a buffer input terminal and a buffer output terminal. A multiplexer is adapted to selectively couple an IC input terminal to the buffer input terminal or to couple the buffer output terminal to the buffer input terminal.

Power management for integrated circuits such as programmable logic devices

In one embodiment, a programmable logic device includes a first multiplexer; a first memory adapted to store an identification code of the programmable logic device; and a second memory adapted to store an identification code of the programmable logic device. Inputs of a second multiplexer are coupled to the first memory and the second memory, and an output of the multiplexer is coupled to an input of the first multiplexer. The second multiplexer is adapted to select between the identification code stored in the first memory and the identification code stored in the second memory to provide the selected identification code to the first multiplexer.

Programmable logic devices with custom identification systems and methods

A programmable logic device, in accordance with an embodiment, includes a first terminal; an input buffer having a buffer input terminal and a buffer output terminal; and a multiplexer coupled to the first terminal and to the input buffer, wherein the multiplexer is adapted to selectively couple either the first terminal to the buffer input terminal or couple the buffer output terminal to the buffer input terminal.

Power management systems and methods for programmable logic devices

Systems and methods are disclosed herein to provide improved non-volatile storage techniques for programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of input/output blocks, and a volatile memory to store data within the programmable logic device, with configuration memory adapted to store first configuration data for configuration of the logic blocks, the input/output blocks, and the volatile memory of the programmable logic device. The programmable logic device further includes a non-volatile memory adapted to store data provided from the volatile memory.

Programmable logic devices with user non-volatile memory

Systems and methods are disclosed herein to provide techniques for providing programmable identification codes (IDCODE) for PLDs. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a first non-volatile memory adapted to store a first identification code of the programmable logic device, and a second memory adapted to store a second identification code of the programmable logic device. A control circuit selects between the first identification code stored in the first non-volatile memory and the second identification code stored in the second memory to provide as an identification code for the programmable logic device.

Systems and methods provide non-volatile memory architectures for programmable logic devices. For example, a programmable logic device may include logic blocks, input/output blocks, and configuration memory to store configuration data for configuration of the logic blocks and the input/output blocks. A first non-volatile memory may store user information, besides configuration data, and a first port includes a dedicated serial peripheral interface to provide access to the first non-volatile memory.

Systems and methods are disclosed herein to provide reconfiguration techniques for PLDs. For example, in accordance with an embodiment of the present invention, a programmable logic device includes logic blocks, input/output blocks, a volatile memory block, and configuration memory cells to store configuration data for configuration of the logic blocks, the input/output blocks, and the volatile memory block of the programmable logic device. The programmable logic device further includes circuit techniques for preventing loss of data stored in the volatile memory block due to a reconfiguration. Furthermore, for example, the programmable logic device may further prevent the loss of data stored in user registers or loss of input/output personality due to the reconfiguration.

Programmable logic devices with transparent field reconfiguration

Systems and methods are disclosed herein to provide an improved approach to the configuration of integrated circuits such as programmable logic devices (PLDs). For example, in accordance with one embodiment of the present invention, a PLD includes volatile memory adapted to store configuration data to configure the PLD for its intended function. The PLD further includes non-volatile memory adapted to store configuration data which is transferable to the volatile memory to configure the PLD for its intended function. The PLD further includes a serial peripheral interface (SPI) port adapted to receive configuration data from an external device for transfer into one of the volatile memory and the non-volatile memory.

Programmable logic device providing a serial peripheral interface

A zero-power electrically erasable and programmable memory cell is implemented in CMOS (complementary metal oxide semiconductor) technology. A P-channel sense transistor has a source coupled to a first voltage generator, and an N-channel sense transistor has a source coupled to a second voltage generator. The drains of the P-channel and N-channel sense transistors are coupled together to form an output of the memory cell, and the gates of the P-channel and N-channel sense transistor are coupled together to form a floating gate of the memory cell. In an example embodiment of the present invention, each of the first and second voltage generators are variable voltage generators that apply a positive voltage at the respective source of each of the P-channel and N-channel sense transistors during the erase operation and/or that apply a ground or negative voltage at the respective source of each of the P-channel and N-channel sense transistors during the program operation. In another embodiment of the present invention, a magnitude of the respective threshold voltage of each of the P-channel and N-channel sense transistors is higher than a magnitude of a threshold voltage of standard process P-channel and N-channel transistors. With such a higher threshold voltage, the P-channel and N-channel sense transistors do not erroneously turn on to dissipate power during the read operation, to ensure that the memory cell is a zero-power memory cell.

Zero-power programmable memory cell

Systems and methods are disclosed herein to provide improved verification of flash memory erasure. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an array of flash memory cells. A plurality of sense amplifiers are also provided wherein each sense amplifier is associated with a plurality of the flash memory cells and adapted to detect a state of one of the associated flash memory cells selected from the plurality of flash memory cells. A first logic circuit is also provided to receive the states of the selected flash memory cells from the sense amplifiers and perform a first logic operation at approximately the same time on the states to verify that all states of the selected flash memory cells correspond to an erased state.

Growing community of inventors

San Jose, CA, United States of America

Fabiano Fontana