Cadence Design Systems, Inc.

Jasper Design Automation, Inc.

Fabiano Cruz Peixoto

Andrea Iabrudi Tavares

Lawrence Loh

Matheus Nogueira Fonseca

Breno Rodrigues Guimaraes

Abner Luis Panho Marciano

Xiaoyang Sun

Artur Melo Mota Costa

Chung-Wah Norris Ip

Craig Franklin Deaton

Björn Håkan Hjort

Thamara Karen Cunha Andrade

Raquel Lara Dos Santos Pereira

Marcus Vinicius Da Mata Gomes

Regina Mara Amaral Fonseca

Breno Rodrigues Guimarães

Alberto Manuel Arias Drake

Laiz Lipiainen Santos

Claudionor José Nunes Coelho, Jr

Patricia Sette Câmara Haizer

Ronalu Augusta Nunes Barcelos

Bruno Andrade Pereira

Tamires Vargas Capanema Franco Santos

Benjamin Chen

Claudionor Coelho, Jr

Caio Araujo Texeira Campos

Tamires Vargas Campanema Franco Santos

Rafael Gontijo Hamdan

Lucas Ferreira De Melo Diniz

Claudionor Jose Nunes Coelho, Jr

Rodolfo Santos Teixeira

Nathália Peixoto Reis

In the described examples, a model impact monitor can include an electronic design automation (EDA) manager that communicates with a plurality of EDA programs, wherein each EDA program generates a model set for a register-transfer level (RTL) design comprising a list of RTL operations. The model impact monitor can also include an adaptive model interface that records changes to the RTL operations of the RTL design and measures a change in performance characteristics of each of the plurality of EDA programs based on a respective one of the changes in the RTL operations of the RTL design.

Adaptive model interface for a plurality of EDA programs

The present disclosure relates to a computer-implemented method for use in an electronic design. The method may include receiving, using at least one processor, an electronic design and analyzing the electronic design. The method may further include generating one or more preconditions representative of metastability effects at the output of at least one synchronizer associated with the electronic design. The method may also include generating, based upon, at least in part, the one or more preconditions, one or more properties configured to analyze a propagation of the metastability effects associated with the at least one synchronizer.

Systems and methods for automatic formal metastability fault analysis in an electronic design

The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and identifying at least one combinational loop associated with the electronic circuit design. Embodiments may also include extracting, for each component of the loop, a set of logic conditions and modeling the at least one combinational loop. Embodiments may further include providing a graphical user interface configured to display one or more constraint candidates and determining whether or not a conflict exists between constraint candidates. Embodiments may also include ranking the constraint candidates, based upon, at least in part, a number of loops disabled and one or more disabled loop characteristics.

System, method, and computer program product for handling combinational loops associated with the formal verification of an electronic circuit design

Disclosed are techniques for verifying an electronic design using hierarchical clock domain crossing verification techniques. These techniques identify an electronic design including a top hierarchy and one or more instances at a first child hierarchy below the top hierarchy. The electronic design may be decomposed into a top hierarchy block for the top hierarchy and one or more child blocks for the one or more instances. A plurality of data structures may be generated by separately processing the top hierarchy block and the one or more child blocks on one or more computing nodes. One or more clock domain crossing structures may be identified in the electronic design at least by integrating the plurality of data structures.

Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniques

Disclosed is an improved approach to implement selective transformations of circuit components for performing verification. The approach looks at the observability of components to downstream properties to determine whether transformations are needed. The verification system leverages the knowledge about the behavior of the domains/components to identify only a subset of components that really need to undergo transformation.

Method and system for implementing selective transformation for low power verification

A method for data propagation analysis. A data propagation diagram for a circuit design is generated. The data propagation diagram includes a plurality of nodes and a plurality of edges connecting the nodes. The nodes represent data locations in the circuit design and the edges represent data propagation paths between the data locations in the circuit design. A signal trace specifying signal values for the circuit design is analyzed to determine whether data at a first data location of the data locations during a first clock cycle is causally related to the data at a second data location of the data locations during a second clock cycle. A visual animation is displayed on the data propagation diagram indicating movement of the data between a first node of the nodes corresponding to the first data location and a second node of the nodes corresponding to the second data location.

Data propagation analysis for debugging a circuit design

Various mechanisms identify an electronic design model and determine a data propagation diagram by receiving a set of path property sources or destinations, determine a set of helper properties for the data propagation diagram by traversing at least a portion of the data propagation diagram, and verify the electronic design model by examining one or more helper properties and determining verification of the one or more helper properties leads to concrete results to generate verification results. Data propagation diagrams may be annotated with verification results to show verification progresses, highlight sources of complexity, and be further synchronized with waveform displays of one or more traces. Search space may be trimmed during a verification flow to enhance performance of verification engine(s). New start states closer to the final state than the default state may be identified during verification and used to enhance performance of the verification engine.

Method, system, and computer program product for verifying an electronic circuit design with a graph-based proof flow

Disclosed are techniques for enhancing formal verification with counter acceleration for electronic designs. These techniques identify at least a portion of an electronic design including a counter having a current counter value and intercept next counter values transmitted to the counter with a counter abstraction module. These techniques further determine whether to accelerate the counter from the current counter value to an engine synthesized next counter value, rather than to an original next counter value based at least in part on a set of critical values. The counter is accelerated from the current counter value to the engine synthesized next counter value when the counter abstraction module determines to accelerate the counter.

Methods, systems, and articles of manufacture for enhancing formal verification with counter acceleration for electronic designs

Various mechanisms and approaches identify a first electronic design component at least by traversing at least a portion of the electronic design and generate a representation of the electronic design by interconnecting one or more duplicated electronic design components within the representation. The first electronic design component may include a destination electronic design component with a backward traversal of the electronic design. One or more fan-in electronic design components may be duplicated into the one or more duplicated electronic design components. One or more CDC effect models are automatically injected into the representation by adding the one or more CDC effect models along one or more paths in the representation. Proof results are generated at least via proving or disproving one or more checkers for the electronic design by verifying or simulating the representation with the one or more CDC effect models that are automatically injected into the representation.

Methods, systems, and computer program product for verifying electronic designs with clock domain crossing paths

An analysis tool that generates properties for a circuit design. The debugging tool receives a circuit design encoded in a hardware description language. The tool identifies portions of the circuit design that correspond to features of interest (e.g., counters, finite state machines, one hot vectors, etc) in the circuit design. Each portion of the circuit design has a cone of influence, and the tool identifies control signals from within the cones of influence. By identifying control signals in this manner, the tool can then generate the properties based on values for the control signals and the identified portions of the circuit design that are obtained from data describing the operation of the circuit design over a number of clock cycles (e.g., simulation data). The result is one or more properties that are likely to represent a relevant behavior of the circuit design.

Generating properties for circuit designs

Growing community of inventors

Belo Horizonte, Brazil

Fabiano Cruz Peixoto