Cree Gmbh

Wolfspeed, Inc.

Macom Technology Solutions Holdings, Inc.

Fabian Radulescu

Scott Thomas Sheppard

Terry Alcorn

Kyle Bothe

Helmut Hagleitner

Chris Hardiman

Daniel Namishia

Kyoung-Keun Lee

Saptharishi Sriram

Dan Namishia

Evan Jones

Lei Zhao

Jia Guo

Jeremy Fisher

William T Pulz

Bruce C Schmukler

Zoltan Ring

Van Mieczkowski

Jennifer Qingzhu Gao

Yueying Liu

Jennifer Duc

Matt King

Elizabeth Keenan

Daniel Etter

A high electron mobility transistor comprises a semiconductor layer structure that includes a channel layer and a barrier layer and source and drain contacts on the semiconductor layer structure. A gate contact and a multi-layer passivation structure are provided on the semiconductor layer structure between the source contact and the drain contact. The multi-layer passivation structure comprises at least first and second silicon nitride layers that have different material compositions. A spacer passivation layer is provided on sidewalls of the first and second silicon nitride layers. A material composition of the spacer passivation layer is different than a material composition of at least one of the layers of the multi-layer passivation structure.

High electron mobility transistors having reduced drain current drift and methods of fabricating such devices

A transistor device includes a semiconductor structure comprising a channel layer and a barrier layer; source and drain contacts on the semiconductor structure; and a gate on the semiconductor structure between the source and drain contacts. A first portion of the barrier layer extending between the source or drain contact and the gate has a first thickness, a second portion of the barrier layer between the gate and the channel layer has a second thickness, and the first thickness is about 1.5 times to 4 times greater than the second thickness. Related methods of fabrication using a looped recess process are also discussed.

Plasma-based barrier layer removal method for increasing peak transconductance while maintaining on-state resistance and related devices

The present disclosure relates to a semiconductor device with isolation and/or protection structures. A semiconductor device can include a substrate, a first transistor and a second transistor, wherein the first transistor and the second transistor are formed on the substrate, and an isolation structure formed on the substrate. The isolation structure can be formed on the substrate between the first transistor and the second transistor. The isolation structure can be configured to isolate the first transistor and the second transistor.

Semiconductor device with isolation and/or protection structures

A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer. A modified access region is provided at an upper surface of the barrier layer opposite the channel layer. The modified access region includes a material having a lower surface barrier height than the barrier layer. A source contact and a drain contact are formed on the barrier layer, and a gate contact is formed between source contact and the drain contact.

Field effect transistors with modified access regions

An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.

Methods for pillar connection on frontside and passive device integration on backside of die

A semiconductor device configured for a radio frequency (RF) application and further configured for passive device integration and/or improved cooling includes a substrate; an active region portion arranged on the substrate, the active region portion includes at least one radio frequency (RF) transistor amplifier; a cavity arranged within the substrate; and one or more radio frequency (RF) devices arranged in the cavity.

Semiconductor having a backside wafer cavity for radio frequency (RF) passive device integration and/or improved cooling and process of implementing the same

A packaged electronic circuit includes a substrate having an upper surface, a first metal layer on the upper surface of the substrate, a first polymer layer on the first metal layer opposite the substrate, a second metal layer on the first polymer layer opposite the first metal layer, a dielectric layer on the first polymer layer and at least a portion of the second metal layer and a second polymer layer on the dielectric layer.

Packaged electronic circuits having moisture protection encapsulation and methods of forming same

A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, a source contact and a drain contact on the barrier layer, an insulating layer on the semiconductor layer between the source contact and the drain contact, and a gate contact on the insulating layer. The gate contact includes a central portion that extends through the insulating layer and contacts the barrier layer and a drain side wing that extends laterally from the central portion of the gate toward the drain contact by a distance &#x393;. The drain side wing of the gate contact is spaced apart from the barrier layer by a distance dthat is equal to a thickness of the insulating layer. The distance &#x393;is less than about 0.3 &#x3bc;m, and the distance dis less than about 80 nm.

Field effect transistor with enhanced reliability

A transistor amplifier package includes a base, one or more transistor dies on the base, first and second leads coupled to the one or more transistor dies and defining respective radio frequency (RF) signal paths, and an isolation structure on the base between the respective RF signal paths. The isolation structure includes first and second wire bonds. The first and second wire bonds may have a crossed configuration defining at least one cross point therebetween. Related wire bond-based isolation structures are also discussed.

Die-to-die isolation structures for packaged transistor devices

A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.

High electron mobility transistors and power amplifiers including said transistors having improved performance and reliability

A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.

Semiconductor die with improved ruggedness

The present disclosure relates to added isolation between transistors in a multiple path amplifier circuit. The multiple path amplifier circuit includes a substrate, a first transistor on the substrate in a first path, and a second transistor on the substrate in a second path. The multiple path amplifier circuit also includes at least one electrical connection associated with the first and the second transistors and positioned to at least partially extend between the first path and the second path.

Integrated doherty amplifier with added isolation between the carrier and the peaking transistors

A transistor device includes a semiconductor layer, a surface dielectric layer on the semiconductor layer, and at least a portion of a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The transistor device includes an interlayer dielectric layer on the surface dielectric layer, and a field plate on the interlayer dielectric layer. The field plate is laterally spaced apart from the gate, and at least a portion of the field plate includes a recessed portion above the aperture in the surface dielectric layer.

Field effect transistor with at least partially recessed field plate

A high electron mobility transistor includes a channel layer, a barrier layer on the channel layer, source and drain contacts on the barrier layer, a gate contact between the source and drain contacts, and a multi-layer passivation structure on the upper surface of the barrier layer between the source contact and the drain contact. The multi-layer passivation structure includes a first passivation layer that comprises a charge dissipation material directly contacts the upper surface of the barrier layer and a second passivation layer comprising a different material than the first passivation layer that also directly contacts the upper surface of the barrier layer. In some embodiments, at least one recess may be formed in the upper surface of the barrier layer and the second passivation layer may be formed within the recesses.

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Chapel Hill, NC, United States of America

Fabian Radulescu