Auburn University

Innophase Inc.

Digital Analog Integration, Inc.

Other

US Government As Represented by the Secretary of the Army

Jds Uniphase Corporation

Fa Dai

Yang Xu

John David Irwin

Hechen Wang

Dongyi Liao

Haoyi Zhao

Gregg Robert Draudt

Michael Fong

Christopher Olin Evans

Manas Chandran Menon

Teddy David Thomas

Stuart Eric Schechter

Harald Quintus-Bosz

Christopher Robert McCaslin

John B Kinnard

Craig Charles Ovans

Klaus Renner

Evan Alton Hutker

Andrew C Goodfellow

Anthony Clegg Parker

Robert Francis Hartmann

John A Deros

Justin David Cumming

Eric Smallwood

Piotr Diduch

Julien Prosper Marc Aknin

John Stadille

Andres Parada

Elias R Samia

Bing Xu

Huyen NguyenNgoc Cam Le

Charles Eugene Stroud

Geoffrey H Goldman

Ruixin Wang

Jianjun Yu

Mark A Pacek

An analog-to-digital converter includes a first converter stage comprising a successive-approximation-register (SAR) analog-to-digital converter (ADC), the SAR ADC being configured for voltage domain quantization, a second converter stage coupled to the first converter stage to quantize residual voltages of the voltage domain quantization, the second converter stage including a ring time-to-digital converter (TDC), and a third converter stage comprising an interpolation TDC, the interpolation TDC being coupled to the second converter stage to provide further time domain quantization.

Hybrid analog-to-digital converter

An analog-to-digital converter includes a first converter stage, a second converter stage coupled to the first converter stage to quantize a residue signal of the first converter stage, and an inter-stage converter disposed between the first and second converter stages. The inter-stage converter is configured to convert between a first domain and a second domain. The inter-stage converter is configured to process the residue signal of the first converter stage such that a range of the residue signal matches a full scale of the second converter stage.

Hybrid analog-to-digital converter with multi-domain signal processing

The present disclosure includes a time-to-digital converter (TDC) based RF-to-digital (RDC) data converter for time domain signal processing polar receivers. Polar data conversion achieves better SNR tolerance owing to its phase convergence near the origin in a polar coordinate. The proposed RDC consists of a TDC for phase detection and an analog-to-digital converter (ADC) for amplitude conversion. Unlike the conversional data converter, the proposed ADC's sampling position is guided by the detected phase result from the TDC's output. This TDC assisted data-converter architecture reduces the number of bits required for the ADC. In addition, oversampling is no longer needed. With precisely controlled tunable delay cells and gain compensator, this hybrid data convertor is capable to directly convert Quadrature Amplitude Modulation (QAM) waveforms and Amplitude Phase Shift Keying (APSK) waveforms directly from the RF signal without down-conversion. Thus, the proposed RDC architecture achieves lower power consumption and better performance comparing with conventional I/Q receivers.

Radio frequency (RF) to digital polar data converter and time-to-digital converter based time domain signal processing receiver

The disclosure of the present application presents a multiple-ring coupled ring oscillator design that employs multiple-ring coupling to achieve improved phase noise by minimizing noise injection from tail current and adjacent rings, while providing additional output phases for multiphase signal generation. In one non-limiting exemplary prototype embodiment, a 1.5 GHz triple-ring coupled ring oscillator achieved measured phase noise of &#x2212;110.5 dBc/Hz at 1 MHz offset, demonstrating phase noise reduction of 7 dB compared with its single-ring oscillator counterpart. The MROs couple multiple rings with proper phase shifting to achieve improved phase noise. Common source coupling benefits from tail current noise reduction, and introducing phase delays in the coupling paths minimizes noise coupling from the adjacent cores. The overall effect leads to improved phase noise performance as demonstrated in quadrature voltage controlled VCO designs. The concept is applied to ring oscillator designs and, as stated previously, demonstrates a triple-ring coupled ring oscillator with phase noise improvement. The design of the present application also triples the number of output phases compared to its single ring oscillator counterpart. The application of injection-locked PLL by using proposed multiple ring coupled ring oscillator achieves the same low phase noise as traditional IL-PLL does while lowering the reference spur at auxiliary ring's output. In another non-limiting exemplary embodiment, the proposed IL-PLL consumes 13.5 mW of power, while achieving in-band phase noise of &#x2212;120.97 dBc/Hz at 1 MHz offset at 1.1 GHz output frequency.

Multi-ring coupled ring oscillator with improved phase noise

Some embodiments include a privacy/security apparatus for a portable communication device that includes a housing assembly configured to at least partially attenuate at least one of sound energy, acoustic energy, and electromagnetic energy including light, optical, and IR energy and RF radiation from passing through the housing assembly. The housing assembly includes a Faraday cage with two or more portions, and at least one protective shell coupled to or forming at least one aperture. The at least one aperture is configured and arranged to at least partially enclose the portable communication device so that at least a portion of the portable communication device is positioned within at least one portion of the Faraday cage, and the at least one seal coupled or integrated with the protective shell. The housing assembly can be an articulating assembly, a sliding assembly, and can include an active acoustic jamming or passive acoustic attenuation element.

Privacy and security systems and methods of use

A digitally controlled oscillator (DCO) modulation apparatus and method provides a wideband phase-modulated signal output. An exemplary modulator circuit uses an oscillator in a phase-locked loop. The circuit receives a wrapped-phase input signal, unwraps the wrapped-phase input signal to generate an unwrapped-phase signal, and differentiates the unwrapped-phase signal. The wrapped-phase input signal and the differentiated unwrapped-phase signal are both injected into a feedback loop of the modulator circuit. The feedback loop may include a multi-modulus frequency divider with a frequency divisor that is temporarily incremented or decremented to cancel out abrupt phase jumps associated with the wrapped-phase to unwrapped-phase conversion.

Wideband direct modulation with two-point injection in digital phase locked loops

An RF system comprising of outputs to an electronically scanning antenna for radiating electromagnetic energy; at least one waveform generator; two multiphase phase-locked loops integrated with the waveform generator, the phase locked loops operating to provide multiple shifted phases to a waveform. Optionally, the two multiphase phase-locked loops may each be divided down by a bank of frequency dividers to further increase the number of phase shifts. The phases generated from each multiphase phase-locked loops are selected with multiplexers then mixed together. These upper or lower sidebands are then mixed with the up converted waveform which results in a phase shift for the waveform associated with each antenna element.

RF system with integrated phase shifters using dual multi-phase phase-locked loops

A time to digital converter (TDC) is able to be utilized for measuring a time interval between two signals with a very fine time resolution, which is defined as the difference in propagation delay per stage between two rings or chains of delay stages. The Vernier ring TDC, Vernier TDC with comparator matrix or Vernier ring TDCs with comparator matrix comprise two rings or chains of delay stages with slightly different propagation delays per stage and a plurality of comparators for comparing two signals propagation along two rings or chains and determining when the lag signal passes the lead signal. The lead and lag signal are initiated by two events and are each fed into a separate one the first stages of one of the specified rings or chains. The comparators are able to be organized in a comparator matrix in order to occupy less space and permit reuse. As a result, the input time interval (the time between the two initiating events) is able to be measured through the product of the time resolution and the number of stages through which the two signals propagated.

Vernier ring time-to-digital converters with comparator matrix

A direct digital synthesis (DDS) circuit utilizes high order delta-sigma interpolators to remove frequency, phase and amplitude domain quantization errors. The DDS employs an n-bit accumulator operative for receiving an input frequency word (FCW) representing the desired frequency output and converts the frequency word to phase information based upon the clock frequency of the DDS. A high-order delta-sigma interpolator is configured in frequency, phase or amplitude domain to noise-shape the quantization errors through a unit defined by the transfer function of 1-(1&#x2212;z)in either a feedforward or feedback manner. The delta-sigma interpolator of any order can be implemented using a single-stage pipelined topology with noise transfer function of (1&#x2212;z). The DDS circuit also includes digital-to-analog converters (DACs) that convert the outputted sine and cosine amplitude words to analog sinusoidal quardrature signals; and deglitch analog low-pass filters that remove the small glitches due to data conversion.

High-order delta-sigma noise shaping in direct digital frequency synthesis

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Auburn, AL, United States of America

Fa Dai