Texas Instruments Corporation

F Scott Johnson

Kelly Jay Taylor

Benjamin P McKee

Tad Grider

Douglas A Prinslow

Douglas Ticknor Grider

Stanton Petree Ashburn

Katherine E Violette

Doug Prinslow

Luigi Columbo

Van-Joy Tsai

Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted in to the exposed gate structure.

Methods for transistor formation using selective gate implantation

Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.

Methods for transistors formation using selective gate implantation

Methods are disclosed for semiconductor device fabrication in which MOS transistor gates are to be formed. Polysilicon gate structures and sidewall spacers are formed, with upper portions of the gate sidewalls exposed. Angled implantation processing is employed to impart dopants to the top and exposed sidewall portions of the gate structure to mitigate poly depletion.

Methods for transistor gate formation using gate sidewall implantation

Disclosed is a system for fabricating an integrated circuit capacitor ( ). An electrode layer ( ) is formed in the integrated circuit. An anti-reflective coating ( ) is deposited over the electrode layer ( ). An electrode top plate ( ) is formed over the anti-reflective coating ( ).

System for fabricating a metal/anti-reflective coating/insulator/metal (MAIM) capacitor

A capacitor ( ) having a bottom plate ( ) that includes undoped polysilicon ( ) which has been silicided ( ). An advantage of the invention is providing a capacitor ( ) having reduced parasitic capacitance to the substrate ( ) and reduced sheet resistance of the bottom plate ( ).

Silicided undoped polysilicon for capacitor bottom plate

A lateral NPN transistor (LPNP) ( ) having the lightly doped drain extension implant blocked from the emitter region ( ) but not the collector region ( ). Accordingly, the emitter region ( ) has a more abrupt junction for high emitter injection efficiency while the collector region ( ) has a lightly doped region for reduced base depletion.

Advanced lateral PNP by implant negation

A method for fabricating inductors and transformers on integrated circuits. A magnetic material is formed on the semiconductor substrate. The magnetic material comprises a suspension of magnetic material in an insulator. A metal film is formed that forms at least one coil around the magnetic material forming an inductor structure. Two adjacent coils can be linked with the magnetic material to form a transformer.

Method of fabricating a miniaturized integrated circuit inductor and transformer fabrication

A capacitor ( ) having a bottom plate ( ) that comprises undoped polysilicon ( ) which has been silicided ( ). An advantage of the invention is providing a capacitor ( ) having reduced parasitic capacitance to the substrate ( ) and reduced sheet resistance of the bottom plate ( ).

A lateral PNP transistor (LPNP) (,) having the low resistance base buried N&plus; region (,) removed from below the emitter region (,). This leaves a high resistance n-well (,) below the emitter. The resistance from the center of the emitter region (,) to the N&plus; buried region (,) is greater than the resistance at the periphery of the emitter region (,) to the N&plus; buried region (,). Debiasing will occur in the center of the emitter region (,) where the parasitic base current is generated. Thus, the ratio of parasitic current to active collector current and peak beta will improve.

LPNP utilizing base ballast resistor

A bipolar transistor includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region. and a base link-up region within the collector region between the intrinsic base region and the extrinsic base region. An emitter region is positioned within the intrinsic base region. A base electrode overlays and is in electrical communication with a portion of the extrinsic base region and the base link-up region, and a doped inter-polysilicon dielectric layer overlays a portion of the base electrode. A capping layer is positioned above the inter-polysilicon dielectric layer; and an emitter electrode overlays the inter-polysilicon dielectric layer and the emitter region. The doped inter-polysilicon dielectric layer is the dopant source for forming the extrinsic base region and the base link-up region.

Self-aligned BJT emitter contact

An emitter contact structure, and associated method, for a bipolar junction transistor. The emitter contact structure includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region, a base link-up region within the collector region between the intrinsic base region and the extrinsic base region, a base link diffusion source layer above the base link-up region, a capping layer above the base link diffusion source layer, and a base electrode laterally engaging the extrinsic base region.

Self-aligned transistor contact for epitaxial layers

A bipolar transistor includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region, and a base link-up region within the collector region between the intrinsic base region and the extrinsic base region. An emitter region is positioned within the intrinsic base region. A base electrode overlays and is in electrical communication with a portion of the extrinsic base region and the base link-up region, and a doped inter-polysilicon dielectric layer overlays a portion of the base electrode. A capping layer is positioned above the inter-polysilicon dielectric layer; and an emitter electrode overlays the inter-polysilicon dielectric layer and the emitter region. The doped inter-polysilicon dielectric layer is the dopant source for forming the extrinsic base region and the base link-up region.

Method for forming a self-aligned BJT emitter contact

An embodiment of the instant invention is a method of fabricating a semiconductor device which includes a dielectric layer situated between a conductive structure and a semiconductor substrate, the method comprising the steps of: forming the dielectric layer (layer 14) on the semiconductor substrate (substrate 12); forming the conductive structure (structure 18) on the dielectric layer; doping the conductive structure with boron; and doping the conductive structure with a dopant which inhibits the diffusion of boron. The semiconductor device may be a PMOS transistor or a capacitor. Preferably, the conductive structure is a gate structure. The dielectric layer is, preferably, comprised of a material selected from the group consisting of: an oxide, an oxide/oxide stack, an oxide/nitride stack, and an oxynitride. Preferably, the dopant which inhibits the diffusion of boron comprises at least one group III or group IV element. More specifically, it is preferably comprised of: carbon, germanium, and any combination thereof. Preferably, the steps of doping the conductive structure with boron and doping the conductive structure with a dopant which inhibits the diffusion of boron are accomplished substantially simultaneously, or the step of doping the conductive structure with boron is preformed prior to the step of doping the conductive structure with a dopant which inhibits the diffusion of boron are accomplished substantially simultaneously.

Doped polysilicon to retard boron diffusion into and through thin gate

A bipolar transistor (100) and a method for forming the same. A diffusion source dielectric layer (118) is deposited over a semiconductor body (101). An emitter window (116) is then etched through the diffusion source dielectric layer (118). An extrinsic base region (110) is diffused from the diffusion source dielectric layer (118). The intrinsic base region (108) is then implanted. Base-emitter spacers (120) are then formed followed by the emitter electrode (124) and emitter region (126). The extrinsic base region (110) is self-aligned to the emitter eliminating the alignment tolerances for the lateral diffusion of the extrinsic base implant and an extrinsic base implant.

Reduced resistance base contact for single polysilicon bipolar

A bipolar transistor (100) and a method for forming the same. A base-link diffusion source layer (118) is formed over a portion of the collector region (102). The base-link diffusion source layer (118) comprises a material that is capable of being used as a dopant source and is capable of being etched selectively with respect to silicon. A base electrode (114) is formed over at least one end portion of the base-link diffusion source layer (118) and the exposed portions of the base-link diffusion source layer (118) are removed. An extrinsic base region (110) is diffused from the base electrode (114) and a base link-up region (112) is diffused from the base-link diffusion source layer (118). Processing may then continue to form an intrinsic base region (108), emitter region (126), and emitter electrode (124).

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Richardson, TX, United States of America

F Scott Johnson