Growing community of inventors

Glendale, AZ, United States of America

F Michel Brown

Average Co-Inventor Count = 4.88

ph-index = 2

The patent ph-index is calculated by counting the number of publications for which an author has been cited by other authors at least that same number of times.

Forward Citations = 13

F Michel BrownRussell Wayne Guenthner (4 patents)F Michel BrownClinton B Eckard (2 patents)F Michel BrownJohn Edward Heath (2 patents)F Michel BrownAlbert Henry John Wigchert (2 patents)F Michel BrownCynthia S Guenthner (2 patents)F Michel BrownNicholas John Colasacco (2 patents)F Michel BrownStefan R Bohult (1 patent)F Michel BrownSteven G Mehlberg (1 patent)F Michel BrownRodney B Schultz (1 patent)F Michel BrownWilliam J Brophy (1 patent)F Michel BrownF Michel Brown (4 patents)Russell Wayne GuenthnerRussell Wayne Guenthner (38 patents)Clinton B EckardClinton B Eckard (15 patents)John Edward HeathJohn Edward Heath (5 patents)Albert Henry John WigchertAlbert Henry John Wigchert (4 patents)Cynthia S GuenthnerCynthia S Guenthner (3 patents)Nicholas John ColasaccoNicholas John Colasacco (3 patents)Stefan R BohultStefan R Bohult (7 patents)Steven G MehlbergSteven G Mehlberg (1 patent)Rodney B SchultzRodney B Schultz (1 patent)William J BrophyWilliam J Brophy (1 patent)
..
Inventor’s number of patents
..
Strength of working relationships

Company Filing History:

1. Bull Hn Information Systems, Inc. (3 from 302 patents)

2. Other (1 from 832,718 patents)


4 patents:

1. 9754222 - Method for summarized viewing of large numbers of performance metrics while retaining cognizance of potentially significant deviations

2. 8869126 - Method and apparatus enabling multi threaded program execution for a Cobol program including OpenMP directives by utilizing a two-stage compilation process

3. 8370820 - Method and apparatus for enabling parallel processing during execution of a Cobol source program using two-stage compilation

4. 7314491 - Encapsulation of large native operating system functions as enhancements of the instruction set in an emulated central processor system

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as of
12/13/2025
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