Cadence Design Systems, Inc.

F Erich Marschner

Alok Jain

Sandeep Pagey

Yaron Peri-Glass

Axel Siegfried Scherer

Dan Leibovich

Frank Armbruster

A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment on the invention, a plurality of verification scopes of an integrated circuit design as defined as part of a verification plan. A plurality of verification runs are executed within two or more verification scopes defined by the verification plan. At least two verification runs are selected to merge verification results together. Like named scenarios are merged together for each verification scope to generate merged verification results that are then stored into a merge database. A verification report is generated for the integrated circuit design from the merged verification results. A merge point may be specified so like named subtrees and subgroups may be merged across different verification scopes of selected verification runs. The merge point may combine check and coverage results obtained during simulation with check and coverage results obtained during formal verification.

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Ellicott City, MD, United States of America

F Erich Marschner