Xilinx, Inc.

F Erich Goetting

David P Schultz

Steven P Young

John D Logue

Venu M Kondapalli

Scott O Frake

Anthony J Collins

Trevor J Bauer

Lawrence C Hung

Stephen M Trimberger

Bruce E Talley

Raymond C Pang

John E McGrath

Vasisht Mantra Vadi

David Bruce Parlour

Joseph H Hassoun

John K Jennings

Paul Ying-Fung Wu

Patrick J Quinn

Andrew K Percey

Patrick J McGuire

Jennifer Wong

Jeffrey V Lindholm

Jane W Sowards

Ramakrishna K Tanikella

Kwansuhk Oh

Paul G Hyland

P Hugo Lamarche

Marwan M Hassoun

Peter H Alfke

Kameswara K Rao

David Erich Tetzlaff

Schuyler E Shimanek

Moises Emanuel Robinson

Alvin Y Ching

John E Mahoney

Edward S McGettigan

David B Squires

Edel M Young

Jennifer T Tran

Mikael Palczewski

Wade K Peterson

A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second portion non-operational. At a boundary between the two portions, interconnect lines traversing the boundary include a first section in the first portion and a second section in the second portion. The second PLD die includes the first portion of the first PLD die, while omitting the second portion. The interconnect lines extending to the edge of the second die are coupled together in pairs. A software model for both die includes a termination model that omits the pair coupling, adds an RC load compensating for the omitted connection, and (for bidirectional interconnect lines) flags one interconnect line in each pair as being invalid for use by routing software.

Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies

Method and apparatus for a dynamically reconfigurable system monitor () are described. A system monitor () has registers () accessible via a reconfiguration port (). At least one of the registers may be dynamically reconfigured via the reconfiguration port () to select a channel to be monitored or to store an alarm value to be used in monitoring by the system monitor (). Additionally, the system monitor () may be embedded in a columnar block architecture.

Dynamic reconfiguration of a system monitor (DRPORT)

According to particular example embodiments, an integrated circuit includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit. In other particular embodiments involving feedback, phase-locked loop (PLL) signal control and/or delay-locked loop (DLL) signal control is achieved in functional blocks of a programmable logic device (PLD). The PLD is responsive to a source clock and includes a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for at least one of the data transmitters provides a respective target clock.

Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit

Methods of manufacturing a family of packaged integrated circuits (ICs) having at least two different logic capacities. A first IC die includes two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A first set of the first IC dies are packaged such that both portions of the dies are operational. A second set of the first IC dies are packaged such that only the first portion of each die is operational. Once the first and second sets are packaged and the second set of ICs has been evaluated, a decision is made whether or not to manufacture a second IC die that includes the first portion of the first die, while excluding the second portion.

Methods of providing a family of related integrated circuits of different sizes

An integrated circuit die (e.g., a programmable logic device (PLD) die) is manufactured that has the capability of being configured as at least two differently-sized family members. The IC die is tested prior to packaging. If a first portion of the IC die is fully functional, but a second portion includes a localized defect, then the IC die is packaged with a product selection code that configures the IC die to operate as only the first portion of the die. The second portion of the die is deliberately rendered non-operational. Therefore, the IC die can still be sold as a fully functional packaged IC.

Yield-enhancing methods of providing a family of scaled integrated circuits

A method of providing a family of integrated circuits (ICs) includes applying a first product selection code (PSC) to a first IC die, applying a second PSC to a second IC die, and providing a third packaged IC die. The first IC die includes first and second portions, both of which are operational based on the first PSC. The second IC die is a duplicate of the first die, but the second portion is rendered non-operational by the second PSC. The third IC die is substantially similar to the first portion of the first die. The second and third packages can be the same and the packaged dies can be interchangeable in a system. When the dies are programmable logic device (PLD) dies, the second and third dies use the same configuration bit stream, which may be smaller than the configuration bit stream for the first IC die.

Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes

A multi-product integrated circuit die includes at least two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A selection code storage circuit stores a product selection code. A first value of the product selection code selects the option where both the first and second portions of the first die are operational. A second value of the product selection code selects the option where only the first portion of the first die is operational. The selection code storage circuit can include non-volatile memory or a fuse structure, or the product selection code can be configured as a package bonding option. The product selection code can also enable boundary scan for the operational portion of the die, and omit from the boundary scan chain any portions of the die that are deliberately rendered non-operational.

Multi-product die configurable as two or more programmable integrated circuits of different logic capacities

Method and apparatus for a system monitor embedded in a programmable logic device are described. The system monitor includes a dynamic reconfiguration port interface for configuring or reconfiguring the system monitor during operation thereof. The system monitor includes an analog-to-digital converter which is reconfigurable responsive to input via a dynamic reconfiguration port.

System monitor in a programmable logic device

Method and apparatus for an interface to a system monitor () is described. A controller () accessible via a port interface thereof () is configured for read/write access to configuration memory cells () and for read access to status registers (). The configuration memory cells () are addressable via a first address space, and the status registers () are addressable via a second address space different from the first address space. The port interface () is configured to receive a plurality of signals including a data address signal () and a data clock signal (). The data address signal () has address information for accessing either the first address space or the second address space.

Reconfiguration port for dynamic reconfiguration-system monitor interface

Method and apparatus for dynamic configuration of function block logic of an integrated circuit is described. The integrated circuit includes a reconfiguration port coupled to a controller. The controller is coupled to an array of memory cell. A portion of the array of memory cells is coupled for read/write communication with the controller, and another portion of the array of memory cells is not coupled for read/write communication with the controller. The portion of the array of memory cells is configurable at an operational frequency of the integrated circuit for dynamic reconfiguration of the function block logic of the integrated circuit.

Reconfiguration port for dynamic reconfiguration

A digital clock manager is provided. The digital clock manager generates an output clock signal that causes a skewed clock signal to be synchronized with a reference clock signal. Furthermore, the digital clock manager generates a frequency adjusted clock signal that is synchronized with the output clock signal during concurrence periods. The digital clock manager includes a delay lock loop and a digital frequency synthesizer. The delay lock loop generates a synchronizing clock signal that is provided to the digital frequency synthesizer. The output clock signal lags the synchronizing clock signal by a DLL output delay. Similarly, the frequency adjusted clock signal lags the synchronizing clock signal by a DFS output delay. By matching the DLL output delay to the DFS output delay, the digital clock manager synchronizes the output clock signal and the frequency adjusted clock signal.

Synchronized multi-output digital clock manager

Method and apparatus for a system monitor () embedded in a programmable logic device () are described. The system monitor () includes a dynamic reconfiguration port interface () for configuring or reconfiguring the system monitor () during operation thereof. The system monitor () includes an analog-to-digital converter () which is reconfigurable responsive to input via a dynamic reconfiguration port ().

Method and apparatus for sub-frame bit access for reconfiguring a logic block of a programmable logic device is described. A reconfiguration port in communication with a controller is provided. The controller is in communication with configuration memory for configuring the logic block. Configuration information is provided via the reconfiguration port. A single data word stored in the configuration memory is read via the controller, modified with the configuration information, and written back into configuration memory. Accordingly, by reading a single data word, in contrast to an entire frame, on-the-fly reconfiguration is facilitated.

Reconfiguration port for dynamic reconfiguration&#x2014;sub-frame access for reconfiguration

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Cupertino, CA, United States of America

F Erich Goetting