Hewlett-packard Company

F Duncan Terry

George A Haag

Gordon A Greenley

Steve A Shepard

O Douglas Fogg

Frank L Cloutier

Robert N Low

R Ernst Erni

Roy T Buck

Douglas Fogg

A thermal ink jet head is disclosed in which the jetting resistors, fluid interconnections, ink reservoir, electrical connections, and jetting orifices are fully integrated to provide an inexpensive, disposable jetting head. The entire hydraulic ink system is sealed to eliminate user interaction with the liquid ink, and ink can only exit the head via the jetting orifices under the influence of the jetting resistors. Once the ink is expended the user disposes with the old head and installs a new one by breaking and making a simple mechanical and low voltage electrical connection.

Disposable ink jet head

A logic state analyzer monitors an ongoing succession of logic states occurring in a collection of n-many digital signals, and stores in a memory a set of logic states selected from the ongoing succession. A logic state is any one of the 2.sup.n -1 possible patterns the n-many digital signals may exhibit. The memory is of some convenient fixed number of locations, and once the memory is filled the oldest stored logic states are overwritten as the newest logic states are stored. Various storage qualification criteria may be specified, in which case an individual logic state is not stored unless it meets those criteria. Upon recognition of a specified trigger condition in the succession of logic states the logic state analyzer stores an operator selectable number of additional logic states, after which the monitoring and storing of logic states ceases and the stored contents of the memory are displayed. The trigger condition may be the detection of a designated sequence of selected logic states. A sequence detector monitors the ongoing succession of logic states. To satisfy the sequence and thus meet the trigger condition the first logic state in the sequence must occur and be subsequently followed by the next logic state in the sequence, and so on, until all selected logic states in the designated sequence have occurred. It may also be required that each logic state in the sequence be detected a selected number of times before an occurrence of the next logic state in the sequence can contribute toward satisfaction of the sequence. A logic state may be designated as a restart state whose occurrence nullifies any partial satisfaction of the sequence and causes the process of sequence satisfaction to begin afresh.

Logic state analyzer with sequential triggering and restart

A logic state analyzer monitors an ongoing succession of states occurring in a collection of digital signals, and stores in a memory a set of states selected from the ongoing succession. The memory is of some convenient fixed number of locations, and once the memory is filled the oldest stored states are overwritten as the newest states are stored. Various storage qualification criteria may be specified, in which case an individual state is not stored unless the state meets those criteria. Upon recognition of a specified trigger condition in the succession of states the logic state analyzer stores an operator selectable number of additional states. The trigger condition may be as simple as the occurrence of a single specified state or may be as complex as the satisfaction of a sequence of specified states. The resulting collectivity of states stored in the memory may be termed a captured trace. Each of the states in the captured trace is a pattern of logical values for the individual digital signals in the collection thereof. That is, each state is also a bit pattern, and is expressable as a magnitude in a selected radix such as binary, octal, or hexadecimal. The states of the captured trace also possess the natural chronological order in which they were stored into the memory. The captured trace is presented as a graph in cartesian coordinates. The graph is a series of points, each representing a state in the captured trace. The ordinate of each point is the magnitude of the state rendered in a selected radix. The abscissa of each point is the ordinal number indicative of the state's chronological position in the captured trace.

Logic state analyzer with graph of captured trace

The operating modes and parameters of a logic state analyzer are selected by user interaction with a menu displayed upon a CRT. At the highest level of control the user may specify which menu is of interest, should there be more than one. The selected menu is displayed and contains mode selection fields whose labels indicate the various modes that are presently selected. Different modes are selected by positioning a cursor to the associated selection field and then pressing a mode selection key. Each such activation causes the next mode in a sequence of modes, associated with that particular field, to be the selected mode of operation. A descriptive label or phase corresponding to the selected mode is displayed as part of the selection field containing the cursor. The modes and their associated labels are linked in a cyclic order, and repeated activation of the field select key will cycle through the cyclic sequence indefinitely, revealing to the operator what his choices are, as well as indicating the present choice. The cursor may be positioned in random order among several such mode selection fields, but only one field select key is needed, as its above-described action pertains to whichever field contains the cursor. The cursor may also be positioned to parameter entry fields associated with selected modes, and a collection of parameter entry keys allows entry of associated parameters.

Method and apparatus for selecting and setting the mode of operation for

Ongoing succession of states occurring in a collection of digital signals is monitored by a logic state analyzer which stores either all such states or a selected subset thereof meeting certain qualification criteria. The memory into which the states are stored is updated with oldest stored states being overwritten as the newest states are stored, the collectivity of which may be termed a captured trace. The above-mentioned qualification and sequential criteria are termed a trace specification. The utility of such a trace in a logic state analyzer is enhanced by allowing the user to divide the collection of digital signals into groups of related signals, assign symbolic labels to the groups, and indicate a radix for each group. Such division, assignment and indication may be termed a format specification. Subsequent trace specifications as well as the displayed or printed form of the trace itself then incorporate the format specification.

Logic state analyzer with format specification

A logic state analyzer monitors the ongoing succession of states occurring in a collection of digital signals, and stores in a memory either all such states or a selected subset thereof meeting certain qualification criteria. The oldest stored states are overwritten as the newest states are stored. Upon recognition of some trigger condition the logic state analyzer will subsequently store a preselected number of additional states, the collectivity of which may be termed the captured trace. The utility of such a trace in a logic state analyzer is enhanced by equipping the analyzer with a counting mechanism selectively responsive to a high speed clock signal or a programmable state detector. In the former case the counter operates as a timer whose value may represent either the elapsed time between consecutive states in the trace or between each state in the trace and an origin along a time axis. In the latter case the user identifies a state or event of interest and the counter records the number of times that state occurs between the stored states of the trace. In both cases the values of the times or event counts are stored as part of the trace and are displayed in correlated relation to the state data therein.

Logic state analyzer with time and event count measurement between states

A logic state analyzer stores into a data acquisition memory only state data meeting preselected qualification state criteria chosen to weed out state data not of interest among the totality of states occuring within a collection of digital signals. The data acquisition memory retains only the last m-many states stored therein. A selectable integer k, o.ltoreq.k.ltoreq.m, determines how many additional storage operations are performed for qualified state data following the detection of a preselected trigger condition. The actual number of states occurring in the collection of digital signals after the trigger condition but before the storage of the kth qualified data state can be many times the value of k. Qualifying the state data prior to storage allows a modest size data acquisition memory to do the work of a much larger memory and spares the user the task of sorting through much state data known not to be of interest. The preselected qualification criteria may include don't-cares in the definition of the qualification state, as well as the logical OR'ing of a plurality of such qualification states.

Logic state analyzer

A general purpose logic state analyzer selectively stores, formats and displays a digital signal representing a sequence of data states input thereto and provides a graphical display of the stored data states and a count of selected events occurring intermediate to the occurrence of the data states stored. Selective storage of the input data states is provided by comparing the input data states to a preselected sequence of first qualifier state conditions and enabling the storage of input data states in response to the satisfaction of the preselected sequence. Storage is further qualified by storing only data states which individually meet one of a preselected set of second qualifier state conditions. Selective formatting of the stored data states is provided by converting the stored data states in response to selectable assignments of contiguous sets of bits of each stored data state to logical fields, a selectable concatenation of the logical fields, and to radicies selected for each of the respective logical fields. The converted stored data states can be displayed as a formatted listing or as a graphical display. In the graphical display the stored data bits corresponding to a selected logical field are interpreted as a binary magnitude and plotted as the ordinate and the chronological storage location is plotted as the ordinate and the chronological storage location is plotted as the abscissa on a cartesian coordinate system. A count of selected events is obtained from the contents of a binary counter and stored in a second memory in parallel with the storing of each data state. This counter can be incremented selectively in response to either an internal clock or in response to the detection of an input data state satisfying a selected count-qualifier state condition.

Logic state analyzer with graphic display

Logic state analyzer with restart and state occurrence qualification

Apparatus and method for indicating a minimum degree of activity of

A general purpose logic state analyzer selectively stores, formats and displays a digital signal representing a sequence of data states input thereto and provides a graphical display of the stored data states and a count of selected events occurring intermediate to the occurrence of the data states stored. Selective storage of the input data states is provided by comparing the input data states to a preselected sequence of first qualifier state conditions and enabling the storage of input data states in response to the satisfaction of the preselected sequence. Storage is further qualified by storing only data states which individually meet one of a preselected set of second qualifier state conditions. Selective formatting of the stored data states is provided by converting the stored data states in response to selectable assignments of contiguous sets of bits of each stored data state to logical fields, a selectable concatenation of the logical fields, and to radices selected for each of the respective logical fields. The converted stored data states can be displayed as a formatted listing or as a graphical display. In the graphical display the stored data bits corresponding to a selected logical field are interpreted as a binary magnitude and plotted as the ordinate and the chronological storage location is plotted as the ordinate and the chronological storage location is plotted as the abscissa on a cartesian coordinate system. A count of selected events is obtained from the contents of a binary counter and stored in a second memory in parallel with the storing of each data state. This counter can be incremented selectively in response to either an internal clock or in response to the detection of an input state satisfying a selected count-qualifier state condition.

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Meridan, ID, United States of America

F Duncan Terry