Micron Technology Incorporated

Intel Corporation

Round Rock Research, LLC

F Daniel Gealy

Gurtej S Sandhu

Cem Basceri

Thomas M Graettinger

Chris M Carlson

Garo Jacques Derderian

Cancheepuram V Srividya

Scott Jeffrey DeBoer

Vishwanath Bhat

Andrea Gotti

Durai Vishak Nirmal Ramaswamy

Kamal M Karda

Vishnu Kumar Agarwal

Husam N Al-Shareef

Noel Rocklein

Chandra V Mouli

Randhir P S Thakur

Enrico Varesi

Demetrius Sarigiannis

Swapnil Lengade

Randhir P Thakur

Davide Colombo

Innocenzo Tortorelli

Paolo Fantini

Tuman Earl Allen, Iii

David A Korn

John Vernon

Jeff Nelson

Howard E Rhodes

Dale Collins

David K Hwang

Belford T Coursey

Brett W Busch

Kuo-Wei Chang

Dave Chapek

M Noel Rocklein

Sachin V Joshi

George E Beck

Kunal R Parekh

David H Wells

Rishikesh Krishnan

Suraj J Mathew

Marko Milojevic

Zhe Song

Cole S Franklin

Vidya Srividya

Davide Columbo

A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.

Gate-all-around floating-gate field effect memory transistor constructions including ferroelectric gate insulator

Field effect transistor constructions with gate insulator having local regions radially there-through that have different capacitance at different circumferential locations relative to a channel core periphery

Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A memory device, such as a selector device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. A selector device, for instance, may have a composition of selenium, arsenic, and at least one of boron, aluminum, gallium, indium, or thallium. The selector device may also be composed of germanium or silicon, or both. The relative amount of boron, aluminum, gallium, indium, or thallium may affect a threshold voltage of a memory component, and the relative amount may be selected accordingly. A memory component may, for instance have a composition that includes selenium, arsenic, and some combination of germanium, silicon, and at least one of boron, aluminum, gallium, indium, or thallium.

Chalcogenide memory device components and composition

Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element. The memory cell stack further includes an electrode interposed between the at least one of the upper and lower conductive lines and the closer of the first and second active elements.

Structures incorporating and methods of forming metal lines including carbon

A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.

Semiconductor devices including liners, and related systems

A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.

Semiconductor structures including liners comprising alucone and related methods

Memory cells having a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the memory element and a second portion of the memory element. Memory cells having a select device comprising a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the select device and a second portion of the select device. Manufacturing methods are also described.

Memory cells having a number of conductive diffusion barrier materials and manufacturing methods

Semiconductor structures including liners and related methods

Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.

Multi-bit ferroelectric memory device and methods of forming the same

A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof. In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm.

Electrode materials and interface layers to minimize chalcogenide interface resistance

Growing community of inventors

Kuna, ID, United States of America

F Daniel Gealy