International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Marvell Asia Pte., Ltd.

Ezra D B Hall

Sebastian Theodore Ventrone

Mark Alan Lavin

Howard Smith Landis

William C Leipold

Timothy G Dunham

Richard Stephen Graf

Mete Erturk

Kirk David Peterson

Albert Manhee Chu

Jack Robert Smith

Robert E Busch

Theodoros Anemikos

Phillip L Corson

Jed Hickory Rankin

Vibhor Jain

Igor Arsovski

Paul Christian Parries

Kevin A Batson

Alok Vaid

John B DeForge

Nathaniel R Chadwick

Faraydon Pakbaz

Anthony J Perri

Aydin Suren

Clark N Vandam

Paul A Niekrewicz

Daryl M Seizter

An integrated circuit (IC) includes functional logic therein that can be enabled by application of a predefined thermal cycle. The IC includes an enabling fuse operatively coupled to the functional logic, the functional logic being disabled unless enabled by activation of the enabling fuse. A set of thermal sensors are arranged in a physically distributed manner through at least a portion of the IC. A test control macro operatively couples to the set of thermal sensors and the enabling fuse for activating the enabling fuse to enable the functional logic in response to application of a thermal cycle that causes the set of thermal sensors to sequentially experience a thermal condition matching a thermal sequence enabling test. A related method and system for applying the predefined thermal cycle are also provided.

Enabling of functional logic in IC using thermal sequence enabling test

Embodiments of the present disclosure provide an apparatus including mask pattern formed on a mask substrate. A plurality of spatial radiation modulators may be vertically displaced from the mask pattern, and distributed across a two-dimensional area. Each of the plurality of spatial radiation modulators may be adjustable between a first transparent state and a second transparent state to control whether radiation transmitted through the mask pattern passes through each of the plurality of spatial radiation modulators.

Apparatus and related method to control radiation transmission through mask pattern

Chip packages with improved tamper resistance and methods of using such chip packages to provide improved tamper resistance. A lead frame includes a die attach paddle, a plurality of outer lead fingers, and a plurality of inner lead fingers located between the outer lead fingers and the die attach paddle. A chip is attached to the die attach paddle. The chip includes a surface having an outer boundary and a plurality of bond pads arranged proximate to the outer boundary. A first plurality of wires extend from the outer lead fingers to respective locations on the surface of the chip that are interior of the outer boundary relative to the bond pads. A tamper detection circuit is coupled with the first plurality of wires. A second plurality of wires extend from the inner lead fingers to the bond pads on the chip. The second plurality of wires are located between the lead frame and the first plurality of wires.

Tamper detection for a chip package

An IC chip package includes: a base substrate; an interposer substrate including a plurality of wires therein, the interposer substrate operatively coupled to the base substrate; and a processor operatively positioned on the interposer substrate. A memory is operatively positioned on the interposer substrate and operatively coupled to the processor through the interposer substrate. The memory includes: a 3D DRAM stack, a thermoelectric heat pump coupled directly to an uppermost layer of the 3D DRAM stack, and a memory controller operatively coupled to the 3D DRAM stack to control operation of the 3D DRAM stack. A temperature controller operatively coupled to the thermoelectric heat pump controls a temperature of the 3D DRAM stack using the thermoelectric heat pump. A lid may thermally couple to an uppermost surface of the processor and an uppermost surface of the thermoelectric heat pump.

Memory having thermoelectric heat pump and related IC chip package and method

Various embodiments include solutions for analyzing three-dimensional video data. Various embodiments include a system having: at least one sensor for detecting at least one of object occlusion or drift in visual data; and a digital signal processor coupled with the at least one sensor, the digital signal processor having at least one database (DB) including target template sets for analyzing both object occlusion in visual data and drift in visual data, wherein the digital signal processor is configured to switch between one of the target template sets and a distinct target template set in the at least one DB based upon detection of the at least one of object occlusion or drift in the visual data.

Video tracker having digital signal processor

Methods, systems, and structures for stress balancing field effect transistors subject to bias temperature instability-caused threshold voltage shifts. A method includes characterizing fatigue of a location in a memory array by skewing a bit line voltage of the location. The method also includes determining that the location is unbalanced based on the characterizing. Further, the method includes inverting a logic state of the location. Additionally, the method includes changing a value of an inversion indicator corresponding to the location.

Stress balancing of circuits

Various particular embodiments include a method of forming an integrated circuit (IC) device including: forming at least one thermoelectric cooling device over an upper surface of a handle wafer based upon a known location of an elevated temperature region in the IC device; forming a first oxide layer over the handle wafer covering the thermoelectric cooling device; forming a second oxide layer over a donor silicon wafer to form a donor wafer; bonding the donor wafer to the handle wafer at the first oxide layer and the second oxide layer, such that the second oxide layer contacts the first oxide layer on the handle wafer; and forming at least one semiconductor device over the donor silicon wafer side of the donor wafer, wherein the at least one thermoelectric cooling device is located proximate the at least one semiconductor device.

Integrated micro-peltier cooling components in silicon-on-insulator (SOI) layers

Disclosed is a resonator made up of three sections (i.e., first, second and third sections) of a semiconductor layer. The second section has an end abutting the first section, a middle portion (i.e., an inductor portion) coiled around the first section and another end abutting the third section. The first and third sections exhibit a higher capacitance to the wafer substrate than the second section. Also disclosed are a process control system and method that incorporate one or more of these resonators. Specifically, during processing by a processing tool, wireless interrogation unit(s) detect the frequency response of resonator(s) in response to an applied stimulus. The detected frequency response is measured and used as the basis for making real-time adjustments to input settings on the processing tool (e.g., as the basis for making real-time adjustments to the temperature setting(s) of an anneal chamber).

Passive resonator, a system incorporating the passive resonator for real-time intra-process monitoring and control and an associated method

Disclosed are embodiments of a system and a method that allow for wireless and dynamic intra-process (i.e., during and/or between process steps) measurements of integrated circuit parameters. The embodiments incorporate the use of a passive circuit, such as an inductor-capacitor-resistor (LCR) circuit resonator, that has a predetermined sensitivity to process variations in one or more physical or electrical integrated circuit parameters. The passive circuit can be wirelessly interrogated between and/or process steps. Then, the actual behavior exhibited by the passive circuit in response to the interrogation is compared to the expected behavior of an optimal circuit in the absence of process variations in order to determine the one or more parameters. Also disclosed is an embodiment of an exemplary passive circuit that can be used to implement the disclosed system and method embodiments.

System and method for wireless and dynamic intra-process measurement of integrated circuit parameters

Disclosed are embodiments of a pixel imaging circuit that incorporates a standard photodiode. However, the imaging circuit is modified with a feedback loop to provide a first photo response over a first portion of the light sensing range (e.g., at higher light intensity range) and a second reduced-sensitivity photo response over a second portion of the light sensing range (i.e., at a lower light intensity range), thereby extending the circuits dynamic range of coverage. Also disclosed are embodiments of an associated imaging method and a design structure that is embodied in a machine readable medium and used in the imaging circuit design process.

Wide dynamic range image sensor utilizing switch current source at pre-determined switch voltage per pixel

Disclosed are embodiments of a design and manufacturing system and an associated method that allow for design analysis and for insertion, during wafer manufacture, of intra-process monitoring circuitry. These embodiments use a library of pre-qualified intra-process monitoring circuits and a cross-correlation table that links different monitoring circuits with different IC chip components. Specifically, these embodiments analyze integrated circuit chip design data to identify the components designed into the chip. Then, one or more intra-process monitoring circuits are selected from the library and the design data is modified to include the selected monitoring circuit(s).

Integrated circuit chip design flow methodology including insertion of on-chip or scribe line wireless process monitoring and feedback circuitry

An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.

Shapes-based migration of aluminum designs to copper damascene

An interconnect structure for use in semiconductor devices which interconnects a plurality of dissimilar metal wiring layers, which are connected vias, by incorporating shaped voids in the metal layers. The invention also discloses a method by which such structures are constructed.

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Richmond, VT, United States of America

Ezra D B Hall