Motorola Corporation

Freescale Semiconductor,inc.

Ezra Baruch

Yaron Gold

Michael Priel

Dan Kuzmin

Shai Shperber

Dan M Bruck

William C Moyer

Yuval Itkin

Yoav Weizman

Sanjay Wanchoo

Rinatya Levy

An on-die capacitance measurement module (ODCMM) arranged to measure a capacitance element. The ODCMM comprises an oscillating voltage supply that outputs first and second oscillating voltage signals, the first and second oscillating voltage signals comprising differing phases, and the oscillating voltage supply component coupled to a first node of the capacitance element and arranged to provide thereto the first oscillating voltage signal, and a reference voltage component coupled to a second node of the capacitance element to provide a reference voltage signal. The ODCMM operates in a first mode, wherein the reference voltage component is arranged to provide a constant reference voltage to the second node of the capacitance element. The ODCMM is arranged to operate in a second mode, wherein the reference voltage component is arranged to provide a reference voltage signal representative of the second oscillating voltage signal output by the oscillating voltage supply component to the second node of the capacitance element.

On-die capacitance measurement module and method for measuring an on-die capacitive load

A method and device for testing an integrated circuit. The method includes selecting between a shadow latch data retention mode and a shadow latch test mode; performing a first test of an integrated circuit; storing, at the shadow latch if the shadow latch test mode is selected, information representative of a first test-imposed state; performing a second test of the integrated circuit; and generating a test equipment detectable signal if the first test-imposed state differs from a second test-imposed state of the tested latch.

Device and method for testing integrated circuits

A method for testing an integrated circuit, that includes: (a) providing a first signal to a first path that starts within the integrated circuit and ends at a first memory element that is followed by a first IO pad, and providing a second signal to a second path that starts within the integrated circuit and ends at a second memory element that is followed by a second IO pad; (b) comparing between a first test result and a second test result, wherein the first test result represents a state of the first memory element sampled a predefined period after a provision of the first signal and the second test result represents a state of the second memory element sampled a predefined period after a provision of the second signal; (c) altering the predefined period; and (d) repeating the stages of providing, comparing and altering until detecting a time difference between a first path propagation period and a second path propagation period.

Tester and a method for testing an integrated circuit

A system () for testing and failure analysis of an integrated circuit () is provided using failure analysis tools (). An analysis module () having a number of submodule test structures is incorporated into the integrated circuit design. The test structures are chosen in dependence upon the failure analysis tools () to be used. The rest of the integrated circuit contains function modules () arranged to provide normal operating functions. By analysing the submodule test structures of the analysis module () using the failure analysis tools (), physical parameters of the integrated circuit () are obtained and used in subsequent testing of the function modules () by the failure analysis tools (), thus simplifying the testing of the integrated circuit () and reducing the time taken to perform a failure analysis procedure.

Analysis module, integrated circuit, system and method for testing an integrated circuit

A radio (,) having a power supply (,); a power reservoir (,); a plurality of processors (,), having inner registers which store a first flag indicating whether a power failure occurred; a plurality of memory banks (,), coupled to the plurality of processors (,); a power failure sensor (,), coupled to the power supply (,) and to the plurality of processors (,); a power on reset unit (,), coupled to the power failure sensor (,); a clock generator (,), and a power failure recovery controller (,&prime;), coupled to the power supply (,), the energy reservoir (,), the power failure sensor (,), the clock generator (,), the plurality of processors (,) and to the power on reset unit (,). When a short power failure occurs, the power reservoir (,) supplies energy to the radio (,), the power failure recovery controller (,) notifies the plurality of processors (,) that a power failure has occurred, and the plurality of processors (,) write their status to the plurality of memories (,), enter a predetermined state and notify the power failure recovery controller (,) that they enter the predetermined state. After receiving these signals, the power failure recovery controller disables the clock generator, until the power failure ends.

Apparatus with failure recovery and method therefore

An interface (,) in a computer system has an port (,) which is coupled to a memory via a first bi-directional data path (,) and coupled to a peripheral device via a communication path (,). The interface (,) has a controller (,) with an enable portion (,) and a pointer register (,). The pointer register (,) provides a movable pointer (,) to memory entries of data queues. The enable portion (,) continuously receives control signals from the memory (,) and sends enable signals to a port (,). A queue of memory entries is transmitted through the first path (,), the port (,) and the second path (,) or vice versa as long as control signals stored in the queue itself allow a transmission.

Computer system with interface and method

A computer system (100) comprises a processor (110), a memory (300), an interface (101) and peripheral devices (120-1, 120-2, 120-3). The interface has a pointer generator (160), a port (150), a decoder (170), and a parameter register (180). The port (150) transmits data words D(k) (380-k) from the memory (300) to the peripheral devices (120-1, 120-2, 120-3) or vice versa. Communication parameters are stored as parameter sets {P.sub.m } in parameter fields (185-m) of the parameter register (180). The decoder (170) selects a parameter set {P.sub.i } using from control words C(k) stored in the memory (300). Data queues can simultaneously be transmitted to two or more peripheral devices (120-1, 120-2, 120-3).

Interface with selector receiving control words comprising device

An interface (101) in a computer system has an port (150) which is coupled to a memory via a first bidirectional data path (104) and coupled to a peripheral device via a communication path (106). The interface (101) has a controller (170) with a trigger buffer (175) and a pointer register (160). The pointer register (160) provides a movable pointer (165) to memory entries of data queues. The trigger buffer (175) continuously receives and accumulates trigger signals (1 2 3) and sends start signals to the pointer register (165). A queue is transmitted through the first path (104), the port (150) and the second path (106) or vice versa when a first trigger (e.g., (1) signal arrives. The trigger buffer (175) receives further trigger signals (e.g., (2) and accumulates them in a trigger buffer (175) before it sends start signals (e.g., ) for further transmissions. Optionally, interface 101 provides start signals after prioritizing trigger signals.

Growing community of inventors

Karkur, Israel

Ezra Baruch