Honeywell Information Systems Italia

Ezio Cislaghi

Claudio Gentili

Ermanno Maccario

Renzo Pederzini

Alessandro Scotti

A semiconductor memory is provided with means for refreshing the memory. Interrupt requests generated by the memory initiate refreshing cycles, which take place in parallel with normal read/write memory operations. The memory is divided in two parts or blocks. If the central processor unit assigns a cycle for read/write operation to one of the two blocks, the same cycle is utilized to recharge or refresh a row of storage elements of the integrated units which constitute the other block of the memory. Refreshing is regulated by low priority interrupt requests and, if not responded to, by high priority interrupt requests, which are mandatory.

Semiconductor dynamic memory and related refreshing system

A semiconductor memory includes means for separating the causes of error affecting the addressing and recording of information bits from those affecting check, or parity, bits. The recording words comprise 16 information bits, and are divided into two 'bytes', of eight bits each. Each byte is provided with its own check bit; and two half-words of nine bits are recorded at the same address. Each submodule of the memory comprises two printed-circuit cards. The first card supports the integrated memory units wherein, for each word, the information bits of the first byte and the check bit of the second byte are recorded; the second card supports the memory units wherein the information bits of the second byte and the check bit of the first byte are recorded. Since an error cause affecting the control or the addressing circuits mounted on a card does not affect the recording and the addressing circuits of the second card, the recording or addressing of the information bits on one card will differ from the recording and addressing of the related check bit on the other card. Both bytes may be written or read out separately; and the writing or the reading-out signals of the information bits are independent from the writing or reading-out signal of the related check bits for both cards.

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Sedriano (Milan), Italy

Ezio Cislaghi