Motorola Corporation

Freescale Semiconductor,inc.

Eytan Hartung

Oded Yishay

J Greg Viot

Michael E Gladden

James L Broseghini

John P Dunn

Jose A Lyon

Robert J Skruhak

Clarence Coffee

James G Viot

David Shamir

Fernando N Hidalgo

A system-on-chip () includes a 16-bit DSP (), a 16-bit data bus () coupled to the DSP, at least one 32-bit-only peripheral (), a 32-bit data bus () coupled to the peripheral, and a bridge (), including a write merge system (), coupled between the 16-bit and 32-bit buses. A method of the write merge system includes pre-storing addresses of peripherals in a memory map structure (and), receiving 16-bit data and a write transaction from the DSP for modifying sixteen bits of a 32-bit data location of the peripheral; reading 32-bit contents of the data location of the peripheral; multiplexing the received 16-bit data with the read 32-bit contents; and writing a new 32-bit word, including the modified sixteen bits and an unmodified sixteen bits, to the data location of the peripheral, without any intervention from the DSP subsequent to receiving the write transaction.

Performing an N-bit write access to an M&#xd7;N-bit-only peripheral

A display driver circuit (100) includes N scanning drivers (150) for driving a scanning set of display electrodes of a display panel (160) with a set of scanning signals (155), P information drivers (130) for driving an information set of display electrodes of the display panel (160) with a set of information signals (135), and a control section (120) having a first mode and a second mode. In the first mode the control section (120) controls the N scanning drivers (150) to generate N different scanning signals (155). In the second mode the control section controls the N scanning drivers (150) to generate a common scanning signal by S of the scanning drivers (156) and N-S different scanning signals by N-S drivers of the scanning drivers (157), wherein N, P and S are positive integers.

Display driver having a low power mode

A pipelined data processor (10) has a control unit (14') that detects an illegal instruction as well as legal instruction opcodes. An opcode decoder (28) decodes instructions. In response to decoding an illegal instruction, opcode decoder (28) provides no output signal. In response to decoding a legal instruction, opcode decoder (28) provides one of a plurality of output signals. A ROM (27) provides a first output in response to receiving no output from the decoder (28), and provides one of a plurality of second outputs in response to receiving one of a plurality of output signals from decoder (28). The first output of the ROM (27) is a first microword of a routine for processing the illegal instruction. Each of the second outputs of the ROM (27) is a first microword of a routine for processing the legal instruction received from the decoder (28).

Pipelined data processor that detects an illegal instruction by

A method and apparatus for scan testing an array (20) in a data processing system (10). In one form, the present invention uses a scanning sense amplifier (22x) which can perform the three functions of a sense amplifier, a master test latch for scan testing, and a slave test latch for scan testing. Using one scanning sense amplifier (22x) to perform all three functions reduces the amount of circuitry required to scan test an array (20). The same stimulus is applied twice to the array (20); and half of the output data bits are scanned out during each application of the stimulus. One extra output data bit is also scanned out during each application of the stimulus. The end result is a reduction in the circuitry required to perform scan testing.

Method and apparatus for scan testing an array in a data processing

Data processing units (14) within an integrated circuit (10) are connected by a common bus (16). Each data processing unit follows a predetermined protocol for communicating to other data processing units via the common bus (16). Further, predetermined control and/or data processing signals within the common bus (16) are multi-tasked (i.e. function multiplexed) for a normal and special modes of operation. A state machine (21) within each data processing unit (12) controls a clock circuit (23). The state machine (21) has a predetermined state diagram for controlling clock signals associated with the predetermined modes of operation.

Data processing system with shared control signals and a state machine

An interrupt mechanism allows an interrupt request signal to be adjusted to any priority level specified by the user and provides to a CPU an encoded interrupt signal which either indicates that the interrupt priority has been adjusted or identifies a highest prioritized interrupt request when no adjustment in priority is made. A first logic circuit functions to receive a priority adjust request signal and compares the adjust signal with one or more interrupt signals to determine if an adjustment is required. A second logic circuit functions to identify the highest prioritized interrupt request of a plurality of interrupt requests and provides the encoded interrupt signal in response thereto. In one form, the encoded interrupt signal is translated into a value for use in a software exception processing routine within the CPU. The software exception processing routine can perform a variety of user specified functions with the encoded adjusted priority interrupt signal.

Method and apparatus for implementing a priority adjustment of an

An adder circuit that has an encoded carry input, where a bit position weight of the carry input is two, allows the adder circuit to selectively concurrently add a data value of two to a first and a second input data operand of the adder circuit. The adder circuit is also able to add the first and second input data operands with a second carry input that is not encoded. A recoded multiplier combines two partial product calculations into one calculation during only a first partial product calculation operation by using the adder circuit. Partial product calculations are reduced in number during a multiply operation of a data processor.

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Austin, TX, United States of America

Eytan Hartung