Cisco Technology, Inc.

Compass Electro Optical Systems Ltd.

Eyal Oren

Garry Paul Epps

Oded Trainin

Mohammed Ismael Tatar

Cedrik K Begin

David Belz

Michael Laor

Earl T Cohen

Rami Zemach

Doron Shoham

Doron Oz

Vladimir Kolmanovitch

Vladimir Miliavsky

Michael Mesh

Gil Goren

Alexander Zeltser

Niv Margalit

Dalit Sagi

Alon Ratinsky

James Fraser Testa

Dan Zislis

Vladimir Miliavisky

A packet switching system for a packet transfer network, the system having an architecture including a plurality of line cards, each including an ingress path pipeline, with processing elements, and an egress buffer, and an electro-optical In/Out (IO) interconnect coupling the line cards to one another in a full mesh connectivity, in the absence of a switch fabric, wherein the ingress path pipeline of each line card is coupled by means of the electro-optical IO interconnect to the egress buffer of each of the plurality of line cards.

Router and switch architecture

A method of error mitigation for transferring packets over a chip-to-chip data interconnect using a high speed interconnect protocol, the method including grouping a pre-selected number of high speed interconnect protocol words to form a protection frame, adding at least one additional error protection bit to each word in the group, adding a synchronization bit to each word, using the synchronization bit in a first word in each frame for synchronization of the protection frame and detecting and correcting a single bit error in the protection frame using the additional error protection bits, thereby reducing packet drop when the frames are transferred over the high speed data interconnect.

High speed interconnect protocol and method

An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets.

Pipelined packet switching and queuing architecture

Streams of packets are dynamically switched among dedicated and shared queues. For example, when a packet stream is in a maintenance mode (such as to keep a tunnel or packet stream associated with a server active) all packet traffic received over a packet stream is directed into the shared queue while the packet stream is not associated with one of the dedicated queues. In response to a detected change in the packet activity status of packet traffic (e.g., the establishment of a call or an increase in packet traffic, especially desirous of individualized quality of service) over a particular packet stream of the packet streams, the particular packet stream is associated with a particular group of dedicated queues such that at least non-control data traffic received over the particular packet stream is subsequently directed into the particular group of dedicated queues while the particular packet stream remains associated with the particular group of dedicated queues.

Dynamically switching streams of packets among dedicated and shared queues

A lookup table including stored data, the lookup table including a Random Access Memory (RAM) for storing the data, wherein the RAM includes a plurality of windows; and a Ternary Content Addressable Memory (TCAM) for storing indices, each index pointing to the windows, and a method for performing a Longest Prefix Match (LPM) including organizing data in such a lookup table, searching according to a lookup key in the TCAM, receiving a match signal from the TCAM including an index pointing to one of the windows, and searching according to the lookup key in the pointed to window.

Method and apparatus for longest prefix matching

Methods and apparatus are disclosed for generating a result based on a lookup result from a lookup operation using an associative memory and processing based on a discriminator portion of a lookup word. A first lookup operation is performed to generate a lookup result. In one implementation, a second lookup operation is performed based on a discriminator or the lookup result depending on the result of an evaluation, such as whether there was a hit or the lookup result matches a predetermined value. In one implementation, a second lookup operation is performed based on the discriminator, and either the result of the first or second lookup operation is used for subsequent processing. One implementation performs a lookup operation based on a lookup word to generate a lookup result, which is used to retrieve a base address and a bitmap from a memory. A discriminator is identified, and the result is generated based on the discriminator, the bitmap, and the base address, such as by adding to the base address the number of set bits in a range within the bitmap.

Methods and apparatus for generating a result based on a lookup result from a lookup operation using an associative memory and processing based on a discriminator portion of a lookup word

A method for communication includes allocating target bandwidths to two or more packet sources and defining one or more of the packet sources as preferred sources. Quantum values defining maximum amounts of data to be sent during a single scheduling round are defined for the respective packet sources. Repetitive scheduling rounds are performed in order to determine a schedule for processing pending data packets produced by the packet sources. In each scheduling round, all pending packets that are produced by the preferred sources and are within the target bandwidths allocated to the preferred sources are scheduled. Pending packets produced by packet sources other than the preferred sources are scheduled in accordance with the quantum values, within the target bandwidths allocated to the packet sources other than the preferred sources. The pending packets are processed responsively to the schedule. The target bandwidths may comprise, for example, guaranteed bandwidths or excess bandwidths.

Oversubscription of guaranteed bandwidth

An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets. These features can include a recycle path coupling a gather stage circuit and a fetch stage circuit and can include sequence number logic configured to associate sequence numbers with multicast packet headers.

An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports of a network interface. A high priority buffer and a low priority buffer can be assigned to each port of the network interface. The network interface can perform packet prioritization through buffer selection based on priority. High priority packets will be transmitted to an ingress packet processor before low priority packets for a given port.

A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in a multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Using bandwidth management techniques, each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port. The destination linecard may be the same physical linecard as that receiving the inbound packet or a different physical linecard. The transmit path includes a buffer/queuing circuit similar to that used in the receive path and can include another pipelined switch. Both enqueuing and dequeuing of packets is accomplished using CoS-based decision making apparatus, congestion avoidance, and bandwidth management hardware.

Token buckets are used in a computer or communications system for controlling rates at which corresponding items are processed. The number of tokens in a token bucket identifies the amount of processing that is available for the corresponding item. Instead of storing the value of a token bucket as a single value in a single memory location as traditionally done, the value of a token bucket is stored across multiple storage locations, such as in on-chip storage and in off-chip storage (e.g., in a memory device). An indication (e.g., one or more bits) can also be stored on chip to identify whether or not the off-chip stored value is zero and/or of at least of a certain magnitude such that it may be readily determined whether there are sufficient tokens to process an item without accessing the off-chip storage.

Tokens in token buckets maintained among primary and secondary storages

Methods and apparatus are disclosed for using a programmable lookup word generator to produce a lookup word for use by a content-addressable memory. The programmable lookup word generator includes a profile memory which contains instructions on how to build a particular lookup word. The programmable lookup word generator receives a set of information and possibly other operands typically including a profile selection. Based on the profile selection, a set of instructions is retrieved from the profile memory. Control logic uses this set of instructions to build the lookup word by extracting portions of the received information and other operands and ordering these extracted portions possibly with additional information to build the lookup word. The lookup word is then used by a CAM, typically to classify the received set of information and other operands. In one context, the CAM produces a packet classification indication in a communication or computer system.

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Raanana, Israel

Eyal Oren