Synopsys, Inc.

Eyal Odiz

Janet L Olson

Jovanka Ciric Vujkovic

Van E Morgan

Mukund Sivaraman

Lisa R McIlwain

John W Hagerman

Michael S Quayle

Kshama Jambhekar

Patrick Groeneveld

Phillip W Baraona

Techniques and systems for concurrent formal verification of logic synthesis are described. A synthesis tool can write intermediate checkpoint designs that embody the state of an integrated circuit (IC) design under synthesis as optimization progresses. Meanwhile, formal equivalence checking proceeds in parallel with synthesis and checks the intermediate checkpoint designs for equivalence.

Concurrent formal verification of logic synthesis

Systems and techniques are described for producing a synthesized IC design that includes design-for-testability (DFT) circuitry. A register-transfer-level (RTL) representation of an IC design can be received, wherein the RTL representation includes functional logic. Next, DFT logic can be added to the RTL representation, and DFT placement guidance for placing the DFT logic can be generated. Synthesis can be performed on the RTL representation to obtain the synthesized IC design, wherein during synthesis, (1) the functional logic and the DFT logic can be placed, wherein the DFT logic is placed based on the DFT placement guidance, (2) scan chains can be inserted and placed, and (3) the DFT logic can be electrically connected with the scan chains.

Design-for-testability (DFT) insertion at register-transfer-level (RTL)

Systems and techniques are described for optimizing an integrated circuit (IC) design. Some embodiment can perform enumeration on a hardware description language (HDL) description of an IC design to obtain a enumerated IC design that includes at least one technology-independent wide-gate or technology-independent wide-bus, wherein the technology-independent wide-gate represents a logical function that is performed on a variable number of inputs, and wherein the technology-independent wide-bus represents a variable number of signals that are part of a bus. The embodiments can then perform technology-independent IC optimization, synthesis, and technology-dependent IC optimization to obtain an optimized and synthesized IC design.

Optimizing an integrated circuit (IC) design comprising at least one wide-gate or wide-bus

Systems and techniques are described for designing an integrated circuit (IC). Some embodiments identify and preserve slices by using new objects in an IC design data model. One or more IC design representations that are used in an IC design flow may natively support such slice objects. These new objects can enable rapid access and preservation of slices, thereby improving the runtime and/or quality of results (QoR) of an IC design system.

Identifying and using slices in an integrated circuit (IC) design

Systems and techniques are described for designing an integrated circuit (IC). Some embodiments explicitly represent wide-buses as distinct objects in an IC design data model. One or more IC design representations that are used in an IC design flow may natively support such wide-bus objects. These new objects can enable rapid access and preservation of wide-buses, thereby improving the runtime and/or quality of results (QoR) of an IC design system.

Creating and using a wide-bus data structure to represent a wide-bus in an integrated circuit (IC) design

Systems and techniques are described for designing an integrated circuit (IC). Some embodiments explicitly represent wide-gates as distinct objects in an IC design data model. One or more IC design representations that are used in an IC design flow may natively support such wide-gate objects. These new objects can enable rapid access and preservation of wide-gates, thereby improving the runtime and/or quality of results (QoR) of an IC design system.

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Los Altos Hills, CA, United States of America

Eyal Odiz