Intel Corporation

Eyal Hadas

Robert Valentine

Zeev Sperber

Amit Gradstein

Simon Rubanovich

Elmoustapha Ould-Ahmed-Vall

Mark Jay Charney

Bret L Toll

Jesus Corbal

Alexander F Heinecke

Raanan Sade

Menachem Adelman

Gavri Berger

Alexander Gendler

Igor Yanover

Ian M Steiner

Nikhil Gupta

Jose Yallouz

Sagi Meller

Ron Schneider

Krishnamurthy Jambur Sathyanarayana

Shmuel Zobel

Edo Hachamo

Saeed Kharouf

Sumesh Subramanian

Embodiments detailed herein relate to systems and methods to zero a tile register pair. In one example, a processor includes decode circuitry to decode a matrix pair zeroing instruction having fields for an opcode and an identifier to identify a destination matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded matrix pair zeroing instruction to zero every element of a left matrix and a right matrix of the identified destination matrix.

Systems and methods to zero a tile register pair

In one embodiment, a processor includes a current protection controller to: receive instruction width information and instruction type information associated with one or more instructions stored in an instruction queue prior to execution of the one or more instructions by an execution circuit; determine a power license level for the core based on the corresponding instruction width information and the instruction type information; generate a request for a license for the core corresponding to the power license level; and communicate the request to a power controller when the one or more instructions are non-speculative, and defer communication of the request when at least one of the one or more instructions is speculative. Other embodiments are described and claimed.

System, apparatus and method for power license control of a processor

The present disclosure is directed to systems and methods for performing one or more operations on a two dimensional tile register using an accelerator that includes a tiled matrix multiplication unit (TMU). The processor circuitry includes reservation station (RS) circuitry to communicatively couple the processor circuitry to the TMU. The RS circuitry coordinates the operations performed by the TMU. TMU dispatch queue (TDQ) circuitry in the TMU maintains the operations received from the RS circuitry in the order that the operations are received from the RS circuitry. Since the duration of each operation is not known prior to execution by the TMU, the RS circuitry maintains shadow dispatch queue (RS-TDQ) circuitry that mirrors the operations in the TDQ circuitry. Communication between the RS circuitryand the TMU provides the RS circuitry with notification of successfully executed operations and allows the RS circuitry to cancel operations where the operations are associated with branch mispredictions and/or non-retired speculatively executed instructions.

Accelerator systems and methods for matrix operations

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Haifa, Israel

Eyal Hadas