Motorola Corporation

Eyal Fayne

David Pincu

Gadi Shirazi

A phase lock loop comprises a phase detector (11), a frequency adjuster (13, 15) for adjusting and cancelling phase differences detected by said phase detector (11) and responsive thereto, and a filter (12) coupled between said phase comparator (11) and said frequency adjuster (13, 15). The phase lock loop has a first and a second operating mode (FIG. 5). Operation in said first operating mode is used to establish an initial lock acquisition to a desired output signal f.sub.out and uses a relatively wide bandwidth within the filter (12). At a transition from said first operating mode to said second operating mode, initial lock acquisition is lost, whereafter said second operating mode is used to re-establish final lock acquisition to the desired output frequency f.sub.out. A gain adjuster (15) commences the controlled adjustment of the gain of said phase comparator (11) at a transition between said first and said second operating modes. Moreover, said gain adjuster (15) adjusts the gain of said phase detection means (11) in a gradual manner defined by a decreasing function whereby the bandwidth of the filter (12) is controllably reduced to substantially that of a relatively narrow bandwidth at a time after lock acquisition has been re-established.

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Givatayim, Israel

Eyal Fayne