Imec Vzw

Sony Semiconductor Solutions Corporation

Ewout Martens

Jan Craninckx

Benjamin Hershberg

Davide Dermit

Keigo Bunsen

Nereo Markulic

Jorge Luis Lagos Benites

Shun Nagata

A slope analog-to-digital converter, ADC, for converting an analog input signal to a digital representation, said slope ADC comprising: a comparator configured to compare two input signals, wherein a sampled value of the analog input signal and a slope signal are used in forming the two input signals; a memory element, which is configured to receive a trigger signal based on the comparator identifying a change in which of the two input signals is higher, and a counter signal, wherein a value of the counter signal when the trigger signal is received provides the digital representation of the sampled value of the analog input signal; wherein the slope signal and the counter signal have a nonlinear relationship, wherein the nonlinear relationship is adapted to improve linearity of a transfer function of the slope ADC for converting the analog input signal to the digital representation.

Slope analog-to-digital converter, a system and a method for converting an analog input signal to a digital representation

There is provided an analog-to-digital converter circuit including: a first converter circuit generating a first digital code by performing analog-to-digital conversion on the basis of an input voltage; a second converter circuit generating a second digital code by performing, on the basis of the input voltage and the first digital code, analog-to-digital conversion over a voltage range wider than that of a least significant bit of the first converter circuit; an error detector detecting a conversion error of the analog-to-digital conversion on the basis of the first and second digital codes, thereby generating error data indicating a bit having a conversion error and the kind of the conversion error; and a calibration circuit estimating an error factor on the basis of the first and second digital codes and the error data, and performing calibration of a circuit relevant to the estimated error factor on the basis of an estimation result.

Analog-to-digital converter circuit

A slope analog-to-digital converter, ADC, comprises: an input unit comprising a sampling capacitor, wherein the input unit is configured to during an initial period obtain a sampled value of an analog input signal and, during a conversion period, hold the sampled value across the sampling capacitor; and a comparator configured to determine a most significant bit of the analog input signal during the initial period; wherein the ADC during the conversion period is configured to receive a slope signal and to be adapted based on the determined most significant bit such that the comparator is further configured to adaptively compare the sampled value and the slope signal for converting the sampled value to a digital representation.

Slope analog-to-digital converter and a method for analog-to-digital conversion of an analog input signal

Example embodiments relate to time-interleaved analog-to-digital converters and conversion methods thereof. One embodiment includes a slope analog-to-digital converter. The slope analog-to-digital converter includes a sample and hold stage configured to sample an analog input signal at a sampling frequency. The slope analog-to-digital converter also includes a comparator downstream to the sample and hold stage configured to compare the analog input signal to a slope signal. Further, the slope analog-to-digital converter includes a digital logic configured to receive a counter value corresponding to a voltage level of the slope signal and to sample the counter value based upon the comparison, thereby generating a digital representation of the analog input signal based upon the comparison. The slope signal is asynchronous to the sampling frequency.

Time-interleaved analog-to-digital converter and conversion method thereof

A device for buffering a reference signal comprises a regulator circuit configured to generate at least two replicas of the reference signal as regulated output signals. The device further comprises a receiving circuit configured to receive the regulated output signals in a switchable manner. In this context, the regulated output signals are configured to have different performance characteristics.

Device and method for enhancing voltage regulation performance

An successive approximation register analog-to-digital converter is provided. The successive approximation register analog-to-digital converter includes a digital-to-analog converter, a successive approximation register, a comparator, and a threshold voltage determining unit. In this context, the threshold voltage determining unit is configured to dynamically determine the threshold voltage of the comparator on the basis of the input signal of the digital-to-analog converter or the output signal of the comparator.

Advanced successive approximation register analog-to-digital converter and corresponding method

A multiplying digital-to-analog conversion circuit for use in an analog-to-digital converter is disclosed. In one aspect, the circuit comprises an input block including a capacitor and arranged for switchably connecting a first terminal of the capacitor to an input voltage signal during a first phase and to a fixed reference voltage during a second phase, a sub-analog-to-digital conversion circuit connected to a second terminal of the capacitor and arranged for quantizing a voltage on the capacitor during the second phase, a sub-digital-to-analog conversion circuit that receives the quantized version of the voltage and outputs an analog voltage derived from the quantized version, a feedback block including an amplifier connected to the second terminal of the capacitor and producing, at an amplifier output during a third phase, a residue signal corresponding to a combination of the input voltage signal and the analog voltage, and a feedback circuit.

Multiplying digital-to-analog conversion circuit

The disclosed technology relates to a method for improving performance of a feedback circuit comprising an amplifier and a feedback network, wherein the feedback circuit has at least one tunable component. In one aspect, the method comprises measuring first amplitude values at an input of the amplifier and second amplitude values at an output of the amplifier, estimating a linear open-loop gain of the amplifier based on both the amplitude values, estimating a linear finite gain error based on the estimated gain and the second amplitude values, subtracting the linear finite gain error from the first amplitude values to derive a set of samples containing second error information, deriving an signal-to-noise-plus-distortion ratio estimate based on the variance of the set of samples and a variance of the second amplitude values, and adjusting the feedback circuit in accordance with the signal-to-noise-plus-distortion ratio estimate.

Method for improving feedback circuit performance

A SAR DAC architecture is disclosed. In one aspect, the SAR DAC architecture uses two parallel DACs for performing a comparison and feedback simultaneously. While one DAC executes a feedback step, the output of the other DAC is used as input for a comparator. For fast operation, the comparator performs the comparison with a reference voltage that has a positive or negative offset from a mid-scale value. The sign of the offset is determined by a previous comparison step. As a result, the same delay can be used for each DAC feedback and comparison, reducing the total conversion time to the time needed for N comparisons for an N-bit architecture, which is a reduction of almost a factor of 2 compared to the conventional SAR architecture.

Analog-to-digital converters

The present disclosure relates to an input circuit comprising positive and negative branches, each branch comprising a transistor arranged for receiving an input voltage at its gate terminal and a first fixed voltage at its drain terminal via a first switch characterized in that the source terminal of the transistor in each of the positive branch and the negative branch is connectable via a second switch to a first plate of a first capacitor in the positive branch and of a second capacitor in the negative branch, respectively, with a second plate of the first capacitor and of the second capacitor being connected to a second fixed voltage and the input circuit further being arranged for receiving a first reset voltage on the first plate of the first capacitor in the positive branch and a second reset voltage on the first plate of the second capacitor in the negative branch.

Input circuit for a dynamic comparator

The disclosure relates to a circuit for stabilizing a digital-to-analog converter reference voltage. One example embodiment is a circuit for stabilizing a voltage on a reference node. The circuit includes a digital-to-analog converter that includes an array of capacitors and arranged for: receiving an input voltage via an input node, receiving a voltage via a reference node and a digital-to-analog code via a controller node, and outputting a digital-to-analog output voltage. The circuit also includes a capacitive network on the reference node comprising a fixed capacitor arranged to be pre-charged to an external reference voltage and a variable capacitor arranged to be pre-charged to an external auxiliary voltage. Further, the circuit includes a measurement block. In addition, the circuit includes a calibration block arranged for determining an updated setting of the variable capacitor based on the digital-to-analog code and the measured voltage on the reference node.

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Heverlee, Belgium

Ewout Martens