Nxp Usa, Inc.

Freescale Semiconductor,inc.

Semiconductor Components Industries, LLC

Other

Evgueniy Nikolov Stefanov

Jean-Michel Francis Reynes

Zia Hossain

Moaniss Zitouni

Edouard D De Fresart

Mohamed Imam

Joe Fulton

Patrice Besse

Ganming Qin

Michael F Petras

Pascal Kamel Abouda

Pon Sung Ku

Philippe Dupuy

Dragan Zupac

Ivana Deram

Rene Escoffier

Yoshio Enosawa

Katsuya Yamazaki

Masami Tanaka

Taku Yamamoto

Mohammed Tanvir Quddus

Francine Y Robb

Rouying Zhan

Laurent Guillot

Peter J Zdebel

Jeffrey Pearse

Edouard De Frésart

Philippe Lance

Jean Philippe Laine

Alain Salles

Jean-Philippe Laine

Jean Michel Reynes

Alain Deram

Yann Weber

Jean-Michel Reynes

Isabelle Majoral

Jean-Pierre Pujo

Hubert Michel Grandry

Edouard Denis De Fresart

An integrated electro-static discharge (ESD) device has a set of metal layers. Each metal layer in the set has one or more first-terminal metal features interleaved with one or more second-terminal metal features in a lateral direction, and at least one first-terminal metal feature in a metal layer of the set overlaps in a normal direction at least one second-terminal metal feature in an adjacent metal layer of the set. By overlapping metal features in the normal direction, capacitance can be added to the ESD device, which improves its operating characteristics, without increasing the layout size of the ESD device.

Electro-static discharge device with integrated capacitance

There is disclosed herein an SOI IC comprising an integrated capacitor comprising a parallel arrangement of a metal-insulator-metal, MIM, capacitor, a second capacitor, a third capacitor, and a fourth capacitor: wherein the second capacitor comprises as plates the substrate and a one of a plurality of semiconductor layers having an n-type doping, and comprises the buried oxide layer as dielectric; the third capacitor comprises as plates the polysilicon layer and a further one of a plurality of semiconductor layers having an n-type doping, and comprises an insulating layer between the plurality of semiconductor layers and the metallisation stack as dielectric; andthe fourth capacitor comprises as plates the polysilicon plug and at least one of the plurality of semiconductor layers and comprises the oxide-lining as dielectric, wherein the oxide lining and the polysilicon plug form part of a lateral isolation (DTI) structure.

Integrated capacitors in an integrated circuit

An ESD protection device for protecting an integrated circuit against an ESD event includes a first terminal coupled to an input/output pad of the IC, a second terminal coupled to a reference or ground voltage, a silicon-controlled rectifier device having an anode connected to the first terminal and a cathode connected to the reference or ground voltage, and a pnp transistor coupled in parallel with the SCR device. The pnp transistor has an emitter coupled to the first terminal, a collector coupled to the second terminal, and a base coupled to a gate of the SCR. The pnp transistor includes a contact region formed at a first side of a substrate, the first contact region being surrounded by an STI layer formed at the first side of the substrate. An insulation structure is formed at an intersection of the first contact region and the STI layer.

ESD protection device, semiconductor device that includes an ESD protection device, and method of manufacturing same

An electrostatic discharge protection device includes a substrate, first and second emitter regions disposed in the substrate, laterally spaced from one another on a side of the substrate, and having opposite conductivity types, and first and second base regions having opposite conductivity types and in which the first and second emitter regions are disposed in a thyristor arrangement, respectively. The first base region includes a buried doped layer that extends under the second base region. Each of the buried doped layer and the second base region includes a respective non-uniformity in dopant concentration profile. A spacing between the buried doped layer and the second base region at the respective non-uniformities establishes a breakdown trigger voltage for the thyristor arrangement.

Unidirectional ESD protection with buried breakdown thyristor device

Semiconductor device and methods for making the devices includes a buried layer of a first conductivity in a substrate in which a distance between two adjacent ends can be selected to achieve a desired breakdown voltage. A deep well having a first doping concentration of a second conductivity type is implanted in an epitaxial layer above the two adjacent ends of the buried layer. A patterned doped region is formed in the deep well and extending into the epitaxial layer above and separated a distance from the two adjacent ends of the buried lay. The patterned doped region has a second doping concentration of the second conductivity type that is greater than the first doping concentration.

Semiconductor device suitable for electrostatic discharge (ESD) protection

A body-control-device for a bi-directional transistor, said bi-directional transistor having a first-transistor-channel-terminal, a second-transistor-channel-terminal, a transistor-control-terminal and a transistor-body-terminal. The body-control-device comprises a body-control-terminal connectable to the transistor-body-terminal of the bi-directional transistor, a first-body-channel-terminal connectable to the first-transistor-channel-terminal of the bi-directional transistor, a second-body-channel-terminal connectable to the second-transistor-channel-terminal of the bi-directional transistor, a negative-voltage-source and a switching-circuit configured to selectively provide an offset-first-circuit-path between the first-body-channel-terminal and the body-control-terminal, wherein the offset-first-circuit-path includes the negative-voltage-source such that it provides a negative voltage bias between the body-control-terminal and the first-body-channel-terminal.

Body-control-device for a bi-directional transistor

Embodiments of a transistor control device for controlling a bi-directional power transistor are disclosed. In an embodiment, a transistor control device for controlling a bi-directional power transistor includes a resistor connectable to a body terminal of the bi-directional power transistor and a transistor body switch circuit connectable to the resistor, to a drain terminal of the bi-directional power transistor, and to a source terminal of the bi-directional power transistor. The transistor body switch circuit includes switch devices and alternating current (AC) capacitive voltage dividers connected to control terminals of the switch devices. The AC capacitive voltage dividers are configured to control the switch devices to switch a voltage of the body terminal of the bi-directional power transistor as a function of a voltage between the drain terminal of the bi-directional power transistor and the source terminal of the bi-directional power transistor.

Circuit arrangement for fast turn-off of bi-directional switching device

A semiconductor device comprises a first contact layer, a first drift layer adjacent the first contact layer, a buried body layer adjacent the first drift layer and a second contact layer. A first vertical trench and a second vertical trench are provided, the first and second vertical trenches being spaced with respect to each other and extending from the second contact layer to substantially beyond the buried body layer. A second drift layer is also provided and sandwiched between the buried body layer and the second contact layer.

Semiconductor device and method of manufacture therefor

A bi-directional trench field effect power transistor. A layer stack extends over the top surface of the substrate, in which vertical trenches are present. An electrical path can be selectively enabled or disabled to allow current to flow in opposite directions through a body located laterally between the first and second vertical trenches. A shallow trench, more shallow than the first vertical trench and the second vertical trench is located between the first vertical trench and the second vertical trench and extend in the vertical direction from the top layer of the stack into the body, beyond an upper boundary of the body. The body is provided with a dopant, the concentration of the dopant is at least one order of magnitude higher in a region adjacent to the shallow trench than near the first vertical trench and the second vertical trench.

Bidirectional power transistor with shallow body trench

A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

Bidirectional trench FET with gate-based resurf

A semiconductor device arrangement comprises a semiconductor device and an injector device. The semiconductor device comprises a first current electrode region of a first conductivity type, a second current electrode region of the first conductivity type, a drift region between the first and the second current electrode regions, and at least one floating region of a second conductivity type formed in the drift region. The injector device is arranged to receive an activation signal when the semiconductor device is turned on and to inject charge carriers of the second conductivity type into the drift region and the at least one floating region in response to receiving the activation signal.

Semiconductor device and method of forming a semiconductor device

A method of forming a semiconductor device comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate, forming a first region of the first conductivity type in the semiconductor layer, and forming a control region over the semiconductor layer and over part of the first region. A mask layer is formed over the semiconductor layer and outlines a first portion of a surface of the semiconductor layer over part of the first region. Semiconductor material of a second conductivity type is provided to the outlined first portion to provide a second region in the semiconductor layer. The first region and second region are driven into the semiconductor layer so as to form a pre-control region of the first conductivity type extending into the semiconductor layer from the surface and under a portion of the control region and a graded body region of the second conductivity type extending into the semiconductor layer under the pre-control region. A body region is formed by providing semiconductor material of the second conductivity type to the outlined first portion. The body region extends into the pre-control region. A current electrode region is formed in the body region.

A semiconductor device comprises a semiconductor layer, a body region of a first conductivity type formed in the semiconductor layer and extending from a first surface of the semiconductor layer, a first region of a second conductivity type formed in the body region, and a second region of the first conductivity type formed in the body region. The first region extends from the first surface of the semiconductor layer and provides a current electrode region of the semiconductor device. The second region surrounds the first region. The doping concentration of the first conductivity type in the second region is greater than a doping concentration of the first conductivity type in the body region.

Field-effect semiconductor device and method of forming the same

A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and forming a mask layer over the semiconductor layer. The mask layer outlines at least two portions of a surface of the semiconductor layer: a first outlined portion outlining a floating region in the active area and a second outlined portion outlining a termination region in the termination area. Semiconductor material of a second conductivity type is provided to the first and second outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and a first termination region of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device.

Method of forming a semiconductor device having an active area and a termination area

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Vieille Toulouse, France

Evgueniy Nikolov Stefanov