Intel Corporation

International Business Machines Corporation

Apple Inc.

Semiconductor Components Industries, LLC

Evgeny Shumaker

Gil Horovitz

Ofir Degani

Igal Kushnir

Aryeh Farber

Danny Elad

Elan Banin

Rotem Banin

Run Levinger

Noam Kaminski

Thomas E Morf

Michael Kerner

Ofer Markish

Sharon Malevsky

Roi Carmon

Yair Dgani

Sergey Bershansky

Nisim Machluf

Stefano Pellerano

Kazushige Toriyama

Keishi Okamoto

Assaf Ben-Bassat

Shahar Gross

Alon Cohen

Rotem Avivi

Eshel Gordon

Somnath Kundu

Abhishek Agrawal

Danniel Nahmanny

Igor Gertman

Jahnavi Sharma

Izhak Hod

Tami Sela

A system may include a digital front end (DFE). The DFE may be configured to generate a command signal. The system may also include a sweeper. The sweeper may be configured to generate an intermediate in-phase signal, an intermediate quadrature signal, and a LO signal based on the command signal. In addition, the system may include a mixer. The mixer may be configured to generate a mixed in-phase signal based on the intermediate in-phase signal and the LO signal. The mixer may also be configured to generate a mixed quadrature signal based on the intermediate quadrature signal and the LO signal. Further, the system may include an amplifier. The amplifier may be configured to generate an in-phase signal based on the mixed in-phase signal and an amplification setting. The amplifier may also be configured to generate a quadrature signal based on the mixed quadrature signal and the amplification setting.

Quadrature chirp generation

A TDC circuit configured to receive a reference clock (REF) signal and a signal derived from a LO; generate a plurality of digital values indicative of a measured phase difference between the signal derived from the LO and the REF signal, wherein each of the plurality of digital values are determined from a unique set of a plurality of sets of TDC measurement component quantization levels; generate a combined series of quantization levels based on a combination of the plurality of sets of TDC measurement component quantization levels; and determine a combined digital value from the combined series of quantization levels and at least one of the plurality of digital values to generate an output of the TDC circuit. The combined series of quantization levels may be generated by summing simultaneously occurring levels of each of the plurality of sets of TDC measurement component quantization levels together.

Methods and devices for TDC resolution improvement

A wireless communication device for asymmetrical frequency spreading including a processor configured to receive a frequency band message comprising a maximum difference and a minimum difference, wherein the maximum difference is between a maximum frequency of a sub-band and a signal frequency, and wherein the minimum difference is between the minimum frequency of the sub-band and the signal frequency compare the maximum difference and the minimum difference with each other; and generate a frequency shift based on the comparison.

Methods and devices for asymmetric frequency spreading

An apparatus for generating a frequency estimate of an output signal includes a reference signal generator configured to generate a reference clock signal. The apparatus includes frequency estimation circuitry configured to generate a cycle count based frequency estimation of the output signal based on the reference clock signal and a clock cycle count of the output signal. The frequency estimation circuitry further generates a fractional frequency estimation of the output signal based on the reference clock signal and a plurality of time-to-digital conversion phase samples of the output signal. The frequency estimation circuitry further generates the frequency estimate of the output signal using the cycle count based frequency estimation within a range and a frequency error determined from the fractional frequency estimation. The plurality of time-to-digital conversion phase samples and the cycle count based frequency estimation use a same number of reference clock cycles of the reference clock signal.

High-resolution and agile frequency measurement

An apparatus for generating an output oscillator signal is provided. The apparatus includes a deviation determining circuitry configured to generate a deviation signal based on a first comparison signal and a second comparison signal. Further, the apparatus includes a first oscillator configured to generate the output oscillator signal based on the deviation signal and a second oscillator signal from a second, resonator-based oscillator. The first comparison signal is based on the second oscillator signal or the output oscillator signal. The second oscillator signal has a frequency of at least 1 GHz. The second comparison signal is based on a third oscillator signal from a third oscillator. The third oscillator signal has a frequency lower than 1 GHz.

Apparatus, system and method for generating an output oscillator signal, transceiver, mobile device and base station

Examples relate to a digitally controlled oscillator circuit arrangement, a digitally controlled oscillation means, a method for a digitally controlled oscillator, a digital loop filter circuit arrangement, a digital loop filtering means, a method for a digital loop filter, a phase locked loop circuit arrangement and phase locked loop, a user device and a base station. The digitally controlled oscillator circuit arrangement comprises input circuitry for obtaining a frequency setting signal, the frequency setting signal comprising a plurality of signal components, selection circuitry for selecting one signal component of the plurality of signal components of the frequency setting signal based on an oscillation signal of the digitally controlled oscillator circuit arrangement, wherein the selection circuitry comprises counting circuitry and multiplexing circuitry, signal generation circuitry for generating the oscillation signal based on the selected signal component of the frequency setting signal, and output circuitry for providing the oscillation signal.

Concept for a digital controlled loop and a digital loop filter

Systems, methods, and circuitries are provided to generate a radio frequency (RF) signal having a desired radio frequency f. In one example a frequency synthesizer system includes a clock, an opportunistic phase locked loop (PLL), and an RF PLL. The clock circuitry is configured to generate a clock signal having a frequency f. The opportunistic phase locked loop (PLL) is configured to generate a reference signal having a reference frequency fthat is close to a free-running frequency of an oscillator in the opportunistic PLL. The opportunistic PLL is configured to synchronize the reference signal to the clock signal. The RF PLL is configured to generate the RF signal having the desired radio frequency and to synchronize the RF signal with the reference signal.

Frequency synthesis with reference signal generated by opportunistic phase locked loop

A phase locked loop (PLL) system for mitigating non-linear phase errors stemming from time-variant integral non-linearity of the LO feedback phase quantizer (TDC) is disclosed. The system includes a phase modulation circuit which is configured to generate a plurality of phase shifts for a reference signal; select a phase shift of the plurality of phase shifts and introduce the selected phase shift into the reference signal, thereby modulating the phase difference between the feedback and the reference signal. Alternatively, the above phase modulation can be applied on the feedback signal path, attaining equivalent results. TDC is configured to quantize the phase of the LO feedback signal relative to the shifted reference signal to generate a phase detection signal, effectively modulating the non-linearity contributed error away from the LO center frequency. The phase detection signal is then digitally compensated for the intentional fractional frequency shift to allow the PLL to generate LO signal the desired frequency.

Systems and methods for mitigation of nonlinearity related phase noise degradations

A quadrature based voltage controlled oscillator (VCO) local oscillator (LO) system is disclosed. The system includes a phase detector, a quadrature phase VCO, a quadrature control path, an in-phase control path, and an in-phase VCO. The phase detector is configured to compare and generate phase error between a reference clock and an in-phase VCO output. The quadrature control path configured to generate a quadrature control voltage based on a quadrature VCO output and the in-phase VCO output. The quadrature phase VCO configured to generate the quadrature VCO output based on the quadrature control voltage and the generated phase error. The in-phase control path configured to generate an in-phase control voltage based on the quadrature VCO output and the in-phase VCO output. The in-phase VCO is configured to generate the in-phase VCO output based on the in-phase control voltage and the generated phase error. An all digital dual mode phase locked/phase tracking loop LO generate system is also disclosed.

Quadrature local oscillator signal generation systems and methods

Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by a delay. Gate circuitry generates a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired delay.

Adaptive time-to-digital converter and method

A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.

Time-to-digital converter, digital phase-locked loop, method for operating a time-to-digital converter, and method for a digital phase-locked loop

Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by an incremental delay. Gate circuitry outputs a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the incremental delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired incremental delay.

Systems, methods, and circuitries for synchronizing a first phase locked loop (PLL) with a second PLL are provided. In one example a PLL system includes a first PLL configured to generate a first signal; a second PLL configured to generate a second signal; and phase calculation circuitry. The phase calculation circuitry is configured to calculate a phase of the first signal at a given time; and provide the calculated phase to the second PLL for use by the second PLL in synchronizing a phase of the second with the phase of the first signal.

Phase synchronization between two phase locked loops

A method and apparatus for determining a difference between signal edges in two signals includes a multiple stage converter where each stage determines which of the two signals has an earlier signal edge, outputs a value corresponding to that determination, and then applies a delay to the earlier signal that is equal to half of the delay applied by the next previous stage. The stages examine smaller and smaller intervals to the sought-after signal edge. Each stage includes a plurality of logic elements. If all logic elements in the stage output the same signal, the edge position is clear. If some of the logic elements in the stage vote differently than others in the state due to differences in setup time for the different elements, the edge location has been found within the sensing band of the stage.

Growing community of inventors

Nesher, Israel

Evgeny Shumaker