Intel Corporation

Evgeny Bolotin

Nir Rosenzweig

Hisham Abu Salah

Guy Satat

Joydeep Ray

Blaise B Fanning

Shlomo Raikin

Zvika Greenfield

Julius Yuli Mandelblat

Ariel Berkovits

Eran Shifer

Dannie G Feekes

Interconnect frequency control technologies of adjusting an operating frequency of a communication interconnect between an integrated circuit comprising multiple functional hardware units are described. A power management unit (PMU) is configured to collect workload data from the functional hardware units and determine a workload metric from the workload data. The PMU adjusts an operating frequency of the communication interconnect in view of the workload metric.

Internal communication interconnect scalability

Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.

Hybrid exclusive multi-level memory architecture with memory management

Growing community of inventors

Haifa, Israel

Evgeny Bolotin