Nxp Usa, Inc.

Freescale Semiconductor,inc.

Evgeni Ginzburg

Adi Katz

Eran Glickman

Shai Koren

Ron Treves

Yuval Harari

Noam Sheffer

Moti Dvir

Ron Michael Bar

Ron-Michael Bar

Gil Moran

Roman Nos

Erez Shaizaf

Keren Guy

Shlomit Dorani

A network processor has a 'bi-level' architecture including a classification algorithm level and a single-record search level to search a hash database that stores packet classification information based on packet field values. The classification algorithm level implements multiple different classification algorithm engines, wherein the individual algorithm applied to a received packet can be selected based on a field of the packet, a port at which the packet was received, or other criteria. Each classification algorithm engine generates one or more single-record search requests to search the hash database for classification information based on one or more field values of the received packet or other classification parameters. Each single-record search requests is provided to the single-record search level, which executes the requests at the hash database and returns the corresponding record to the requesting classification algorithm engine.

Hash-based packet classification with multiple algorithms at a network processor

A method and apparatus are provided for classifying received network frames () by extracting frame header data (e.g., n-tuple) which is combined with a key insert value (e.g., embedded prefix value 'OP0, OP0, . . . OP0') to generate a lookup key (), where the key insert value is generated by decoding a key composition rule () to extract a constant value (OP0) and a repeat value (OP1), and then replicating the constant value one or more times specified by the repeat value.

Method and apparatus for coding a user defined constant into a key composition rule using variable length command

In a processing system, a method includes transmitting a timer expiration notification from a timer management component of a processor to one or more other components of the processor in response to expiration of a timer. The method further includes transmitting, from a component of the processor that requested instantiation of the timer, a timer release confirmation message to the timer management component in response to the timer expiration notification, the timer release confirmation message confirming that the component has released the timer. The method also includes preventing reallocation of a timer identifier (ID) associated with the timer to another timer after the expiration of the timer and until receipt of the timer release confirmation message at the timer management component.

Coherent timer management in a multicore or multithreaded system

A temporal-miss handler includes updating a data leaf in a tree-structured database of a communications processor with a plurality of threads. A search for the data leaf includes generating at least one search result for one of the plurality of threads. A sufficiency of a temporal separation, between updating the data leaf and searching for the data leaf, to retrieve the data leaf is determined. Each search result is cleared when the temporal separation is insufficient. A new search is performed when the temporal separation is insufficient.

Tree-search temporal-miss handling

A data processing device includes a hash table management module that sequentially steps through linear address space of the hash table to identify hash chain in sequential address order. Each identified hash chain is evaluated, before identifying a next hash chain, to remove any entries marked for deletion.

System and method for removing hash table entries

Methods and systems are disclosed for non-intrusive debug processing of network frames. For certain embodiments, a frame parser processes frames from a network interface and generates frame metadata. A key generation engine processes each frame and its related metadata to generate a normal key and a debug key. The same key composition rule formats and key generation engine are used to generate the normal key and the debug key to provide non-intrusive debug processing. Frame classification logic compares the normal key to classification tables to determine a frame classification for the received frame. Separate debug comparison logic compares the debug key to debug reference data/masks to generate debug markers for the received frame. The frame classification and the debug markers for each frame are provided to frame marking logic, and a frame processing engine then processes the resulting marked/classified frames.

Methods and systems for non-intrusive debug processing of network frames

Methods and systems are disclosed to embed valid-field (VF) bits into classification keys for network packet frames. The embedded VF bits allow for extracted data from existing fields associated with frame data to be distinguished from default data used for missing fields where this extracted data and default data has been included within a frame classification key generated for a network packet frame. In certain embodiments, a valid-field field extraction command (VF-FEC) causes a key generator to embed VF bits into a frame classification key, and the logic state of the VF bits are used to distinguish extracted data from default data. Further, the disclosed embodiments allow VF bits to be selectively cleared based upon a bit mask applied prior to embedding of the VF bits. Still further, users can define VF-FECs and other field extraction commands (FECs) for key generation through one or more programmable key composition rules.

Methods and systems to embed valid-field (VF) bits in classification keys for network packet frames

A timer distribution module supports multiple timers and comprises: a command decoder arranged to determine expiration times of a plurality of timers; and a timer link list distribution adapter, LLDA, operably coupled to the command decoder. The LLDA is arranged to: receive a time reference from a master clock; receive timer data from the command decoder wherein the timer data comprises at least one timer expiration link list; construct a plurality of timer link lists based on at least one of: the timer expiration link list, at least one configurable timing barrier; dynamically split the link list timer data into a plurality of granularities based on the timer expiration link list; and output the dynamically split link list timer data.

Methods and apparatus for adaptive time keeping for multiple timers

A device and a method for performing bitwise manipulation is provided. Multiple bitwise logic circuits are coupled to an instruction decoder, a register array and a rotator. Each bitwise logic circuit includes input multiplexers connected to an output multiplexer. The instruction decoder receives a bit manipulation instruction and sends to each corresponding input multiplexer a control signal based on a type of the instruction. Each input multiplexer of each bitwise logic circuit receives a control signal, a constant signal that has a value that is indifferent to the value of the mask, and a mask affected signal that has a value that is responsive to a value of an associated mask bit. Each input multiplexer selects between the constant signal and the mask affected signal based on the control signal, and outputs a selected signal. Each output multiplexer receives selected signals from each of the corresponding input multiplexers, and elects between the selected signal based on a value of an associated manipulated register bit and based on a value an associated control register bit.

Device and method for performing conditional bitwise set/clear/toggle manipulations in a general purpose register

A distributed debug system including processing elements connected to perform a plurality of processing functions on a received data unit, a debug trap unit, a debug trace dump logic unit, and a debug initiator unit is provided. At least two of the processing elements include a debug trap unit that has a first debug enable input and output, and a first debug thread. The first debug thread holds at least a first debug trap circuit having a match signal output connected to the first debug enable output. The first debug trap circuit filters a part of the data unit, compares a filtering result with a debug value, and provides a match signal to the match signal output. The debug trace dump logic unit dumps debug trace data to a buffer associated with the data unit on reception of a match event. The debug initiator unit includes a debug initiator output connected to the first debug enable input of the debug trap unit of one processing element, and a debug initiator input connected to the first debug enable output of the debug trap unit of another processing element.

Distributed debug system

A method and a device having a plurality of bit operations capability, the device includes: a first and a second registers and an instruction fetch circuit, and an arithmetic logic unit adapted to: calculate, during a first clock cycle, a position value representative of a position, within a first information vector, of a first bit of information that has a first value; and to multiply the position value by a multiplication factor to provide a first result and to alter the value of the first bit to a second value to provide an updated information vector, during the first clock cycle.

Method for performing plurality of bit operations and a device having plurality of bit operations capabilities

A method for locating an extreme value data chunk within a data block, the method includes: fetching, by a processor, an instruction; fetching, in response to a content of the instruction, a data unit that comprises multiple data chunks; selectively masking the fetched data chunks in response to a value of a mask; comparing, by a hardware accelerator, between values of valid data chunks to provide a extreme value data chunk; wherein valid data chunks include un-masked data chunks that belong to the data block; updating the value of the mask and jumping to the stage of fetching a new data unit, until the whole data block is fetched.

Device and method for finding extreme values in a data block

A method for searching within a data block for a data chunk having a predefined value, the method includes: fetching, by a processor, a data block search instruction; fetching, a data unit that includes multiple data chunks; wherein at least one data chunk within the data unit belongs to the data block; deciding whether to use a mask for data chunk level masking; searching, by a hardware accelerator, for a valid data chunk within the fetched data unit that has the predefined value; wherein the searching comprising applying a mask; wherein a valid data chunk in an non-masked data chunk that belongs to the data block; and determining whether to update the value of the mask and whether to fetch a new data unit that belongs to the data block.

Hardware accelerator based method and device for string searching

A method and a device for processing instructions based on register group size information includes a pipelined processor, an instruction memory unit and a register file, whereas the pipelined processor includes a write-back unit and an execution unit. The device is characterized by including a controller that is adapted to receive a first register group size information and a first register identification information that define a first group of source registers associated with a first instruction; and to determine an execution related operation of the first instruction in response to the first register group size information, the first register identification information, a second register group size information and a second register identification information. The second register group size information and the second register identification information define a second group of target registers associated with a second instruction. The second instruction is provided to the pipelined processor before the first instruction.

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Petah Tikva, Israel

Evgeni Ginzburg