Nxp B.v.

Koninklijke Philips Corporation N.v.

Evert-Jan Daniël Pol

Josephus Theodorus Johannes Van Eijndhoven

Martijn Rutten

Menno Menasshe Lindwer

Henricus Hubertus Van Den Berg

Pieter Van Der Wolf

Om Prakash Gangwal

Geraud Plagne

Hugues Dailliez

A series () of original instructions for a single processor is translated into implementing instructions for executions distributed over a plurality of processors () of different type. The series () of original instructions is split into successive sections (-) assigned to respective ones of the processors (). Operand transfer instructions are added to the sections (-) to support data dependencies between the sections (-). The assignment includes selecting a location of a boundary in the series of original instructions between successive ones of the sections (-) so as to substantially minimize an aggregate of the execution cost factors of the original instructions as implemented and including costs for the operand transfer instructions. Preferably, the locations of the boundaries are determined from a search among different boundaries positions.

Translation of a series of computer instructions

A plurality of digital signal processors (), each contains a signal processing core (), a memory () coupled to the processing core () and a multiplexed data input () coupled to the memory (). Each digital signal processor has a plurality of outputs for outputting data from the signal processing core (). A remote write only structure (-) couples outputs of respective groups of the digital signal processors () each to the multiplexed data input () of respective particular digital signal processor (), the respective group for the particular digital signal processor () not including the particular digital signal processor (). Thus, each processor () writes data for other processors directly from the processor, without storing the data in memory first for handling by an I/O processor, and reads data from other processors () via memory, where it is received via an input that does not share resources with the output of the processor ().

Integrated circuit with a plurality of communicating digital signal processors

Aspects involve effectively separating communication hardware in a data processing system by introducing a communication device for each processor. By introducing this separation the processors can concentrate on performing their function-specific tasks, while the communication device provide the communication support for the respective processor. Accordingly, in certain embodiments, a data processing system is provided with a computation, a communication support and a communication network layer.

Data processing system having multiple processors and a communications means in a data processing system

The dismissing of cached data that is not expected to be further used is predicted instead of predicting future I/O operations and then data is fetched from the main memory to replace the dismissed data in the cache. Thus, firstly a location in a cache memory containing data, which is expected not to be further used, is identified, followed by performing a prefetch operation in order to request new data to refill the above location in the cache memory. Therefore, a data processing system comprises at least one processor () for processing streaming data, at least one cache memory () having a plurality of cache blocks (), wherein one of said cache memories () is associated to each of said processors (), and at least one cache controller () for prefetching data into said cache memory (), wherein one of said cache controllers () is associated to each of said cache memories (). Said cache controller () comprises determining means () for identifying at least one location in said cache memory () containing first data, which is predicted to be dismissible without penalty and prefetch means () for issuing a prefetch operation replacing said first data at said location with second data, which fit said location.

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Eindhoven, Netherlands

Evert-Jan Daniël Pol