U.S. Philips Corporation

Evert D Van Veldhuizen

Adrianus Van Bezooijen

Chi-Tien Chen

Paul S Marston

Hsien C Ou

A digital receiver has a local oscillator that provides a local oscillator signal, a frequency offset detector that provides a frequency offset signal that is representative of a difference between the local oscillator signal and a desired tuning frequency of the digital receiver, and a frequency controller that controls the frequency of the local oscillator on the basis of a stored control value. The frequency controller separately derives a short term drift compensation signal and a long term drift compensation signal from the frequency offset signal, at a first interval updates the stored control value on the basis of the derived short term drift compensation signal, and at a second interval updates the stored control value on the basis of the long term drift compensation signal. The first interval is substantially shorter than the second interval.

Digital communication device

A receiving apparatus has a clock frequency generating circuit comprising in a first embodiment a low cost oscillator whose frequency is higher than the wanted clock frequency and in a second embodiment a low cost oscillator whose frequency can be higher or lower than the wanted clock frequency. By means of subtracting pulses from (first embodiment) or adding/subtracting pulses (second embodiment) to/from the output of the low cost oscillator, a clock frequency is generated which is stable within a specified tolerance range. More particularly, the receiving apparatus comprises a circuit (10,12) for receiving a transmitted signal, a circuit (14, 16) for deriving a repetitive reference signal from the received transmitted signal, clock signal generating circuit (22, 24, 32) for generating a clock signal having a frequency corresponding substantially to a desired frequency, and a circuit (36, 42, 46) for determining whether the clock frequency generated in respective time periods between successive reference signals varies relative to an arbitrarily set value, the circuit providing a control signal which is used to adjust the frequency of the generated clock signal.

Frequency generating circuit

A first information (I) is displayed on a display screen of a display device (5). A vertical and horizontal position of a field of the first information (I) on the display screen is determined by a vertical start pulse (V) and by horizontal start pulses (H), both corresponding to or being extracted from the first information (I). The vertical position of a second information (Oi) on the display screen is determined by counting a certain number of the horizontal start pulses (H). To eliminate any remaining jitter, a time difference (Td) is determined between the active edge of the vertical start pulse (V) and that horizontal start pulse (H) which is nearest to the active edge of the vertical start pulse (V). If this time difference (Td) is smaller than a certain safe margin (Ni), the nearest horizontal start pulse (H) is so close to the active edge of the vertical start pulse (V), that an occurrence of vertical jitter is becoming likely. To avoid a dangerous vertical jitter situation, in a next field, the active edge of the vertical start pulse (V) is shifted in time over a shift period (Di), to obtain sufficient distance between the active edge of the vertical start pulse (V) and the nearest horizontal pulse (H).

Vertical position-jitter elimination

Known is a receiver having a demodulator for intermediate frequency modulated frequency shift keyed signals. The known demodulator applies absolute period time measurements expressing the period of a divided IF-signal into clock pulses of a relatively high frequency reference clock to detect data from a received signal. Such a demodulator is sensitive to frequency drift of the reference clock and has a relatively large power consumption. A receiver is proposed having a demodulator that is arranged to transform the intermediate frequency modulated frequency shift keyed signal into a lower frequency modulated frequency shift keyed signal so that the relative frequency deviation representing the data becomes substantially larger. The demodulator is arranged to determine the demodulated data from the lower frequency modulated frequency shift keyed signal by determining a difference in width of at least two successively measured periods of the lower frequency modulated frequency shift keyed signal and by generating a first logic signal value if the difference has a first polarity and by generating a second logic signal value if the difference has a second polarity.

Receiver, a demodulator, and a demodulation method

Messages consisting of an arbitration field followed by a data field circulate in a single-channel bus system. The stations comprise a storage element for an intended delay time between a locally formed signal transition and a resultant detectable signal transition. The stations also comprise a continuous sequencer for the successive bit cells. When a signal transition is detected, the sequencers are loaded with the position of the storage element, so that they are synchronized. In the case of a transmission operation, the delay is measured, so as to update the contents of the storage element.

Single-channel bus system for multi-master use with bit cell

A programmable counter/timer is responsive to signals on a data line for producing signals on one or more output lines and includes a counter connected to the data line, a comparator connected to said counter for producing a control signal when said counter reaches a stored preselected value, and a qualification unit connected to the comparator, the qualification unit having a register for storing a logic state. The qualification unit is responsive to the control signal and the stored logic state for generating a signal on selected output lines when the counter reaches the predetermined stored value.

Multi-function counter/timer and computer system embodying the same

The invention relates to a single-channel digital communication bus system and to a station for use in such system. Only a single physical interconnection between the stations is present for transferring the data. Bit synchronization is effected either in that the data is self-clocking or by a second, clock lead. The data channel realizes an AND-function. The transmission of a message by a master station is answered by an addressed slave by an acknowledge signal train. The acknowledge signal train has a plurality of bits, inclusive of error protection bits. Error protection may be effected by transmitting a series of mutually identical bits, or by means of a CRC signal subtrain. The acknowledge may be positive, negative or a 'no acknowledge' signal train.

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Eindhoven, Netherlands

Evert D Van Veldhuizen