Micron Technology Incorporated

Intel Corporation

Battelle Energy Alliance, LLC

Everett Allen McTeer

Yongjun Jeff Hu

Jordan D Greenlee

John Mark Meldrim

Rita J Klein

Tsz Wah Chan

Christopher W Petz

John David Hopkins

Swapnil Lengade

Shu Qin

Daniel Billingsley

David Ross Economy

Haoyu Li

Durai Vishak Nirmal Ramaswamy

Lifang Xu

Collin Howder

Yushi Hu

Qian Tao

Christian George Emor

Scott G Meikle

Brenda D Kraus

Chet E Carter

Xiao Li

Russell C Zahorik

Shanming Mou

Matthew J King

Eric Blomiley

Yiping Wang

Luca Fumagalli

Rajesh Balachandran

Travis Rampton

Gurtej S Sandhu

John A Smythe

Nancy M Lomeli

Shuangqiang Luo

Jiewei Chen

Chieh Hsien Quek

Anurag Jindal

Jing Wai Fong

Song Kai Tan

Aaron P Thurber

Memory circuitry comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Charge-passage material is in the conductive tiers laterally-outward of the channel-material strings. Storage material is in the conductive tiers laterally-outward of the charge-passage material. At least one of AlOq, ZrOq, and HfOq is in the conductive tiers laterally-outward of the storage material. At least one of (a) and (b) is in the conductive tiers laterally-outward of the at least one of AlOq, ZrOq, and HfOq, where, (a): MoON, where each of 'x' and “y” is from 0 to 4.0; and (b): MoM, where “M” is at least one of W, a Group 7 metal, and a Group 8 metal; “z” being greater than 0 and less than 1.0. Metal material is in the conductive tiers laterally-outward of the at least one of the (a) and the (b). Memory cells are in individual of the conductive tiers. The memory cells individually comprise the channel material of individual of the channel-material strings, the storage material, the at least one of AlOq, ZrOq, and HfOq, the at least one of the (a) and the (b), and the metal material. Other embodiments are disclosed.

Transistor and memory circuitry comprising strings of memory cells

A microelectronic device includes a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Microelectronic devices, memory devices, and electronic systems

An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

Apparatuses including interconnect structures including dielectric material surrounded by conductive material, and related memory devices

A method used in forming a memory array comprising strings of memory cells comprises forming memory block regions individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a void-space extending laterally-across individual of the memory-block regions. At least one of conductive or semiconductive material is formed in the void-space laterally-outward of individual of the channel-material strings. Conductive molybdenum-containing metal material is formed in the void-space directly against the at least one of the conductive or the semiconductive material and a conductive line comprising the conductive molybdenum-containing metal material is formed therefrom. The at least one of the conductive or the semiconductive material is of different composition from that of the conductive molybdenum-containing metal material. Other embodiments, including structure independent of method, are disclosed.

Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of β-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.

Microelectronic devices and memory devices including conductive levels having varying compositions

Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.

Memories having vertically stacked conductive filled structures

Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. The wordline levels include conductive regions which have a first metal-containing material and a second metal-containing material. The first metal-containing material at least partially surrounds the second metal-containing material. The first metal-containing material has a different crystallinity than the second metal-containing material. In some embodiments the first metal-containing material is substantially amorphous, and the second metal-containing material has a mean grain size within a range of from greater than or equal to about 5 nm to less than or equal to about 200 nm. Charge-storage regions are adjacent the wordline levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

Assemblies which include wordlines having a first metal-containing material at least partially surrounding a second metal-containing material and having different crystallinity than the second metal-containing material

Apparatuses including a conductive contact including a dielectric material surrounded by a conductive material

Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

Assemblies having conductive structures with three or more different materials

A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Microelectronic devices including staircase structures, and related memory devices and electronic systems

Described are methods for forming a tungsten conductive structure over a substrate, such as a semiconductor substrate. Described examples include forming a silicon-containing material, such as a doped silicon-containing material, over a supporting structure. The silicon-containing material is then subsequently converted to a tungsten seed material containing the dopant material. A tungsten fill material of lower resistance will then be formed over the tungsten seed material.

Tungsten structures and methods of forming the structures

Some embodiments include conductive interconnects which include the first and second conductive materials, and which extend upwardly from a conductive structure. Some embodiments include integrated assemblies having conductive interconnects.

Conductive interconnects

A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.

Semiconductor devices comprising threshold switching materials

A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of &#x3b2;-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.

Microelectronic devices including conductive levels having varying compositions, and related memory devices, electronic systems, and methods

Growing community of inventors

Eagle, ID, United States of America

Everett Allen McTeer