Infineon Technologies Ag

Infineon Technologies Austria Ag

Evelyn Napetschnig

Alexander Heinrich

Mark Harrison

Bernhard Weidgans

Thomas Behrens

Kamil Karlovsky

Michael Ehmann

Wolfgang Lehnert

Stefan Woehlert

Johann Gatterbauer

Michael Rogalli

Manfred Mengel

Thomas Fischer

Michael Roesner

Edmund Riedl

Carsten Schaeffer

Werner Robl

Joachim Hirschler

Oliver Humbel

Tobias Schmidt

Oliver Eichinger

Franz Stueckler

Karl Mayer

Paul Frank

Catharina Wille

Michael Sternad

Ulrike Fastner

Frank Wagner

Eric Graetz

Michael Pinczolits

Thomas Rupp

Lim Fong

Gretchen Adema

Jens Brandenburg

Anton Pugatschow

Christoffer Erbert

Harry Walter Sax

Joachim Seifert

Christina Yeong

Julia Zischang

Steffen Orso

Thomas Bertaud

Robert Hartl

Ivan Nikitin

Manfred Schneegans

Holger Schulze

Swee Kah Lee

Markus Beninger-Bina

Kurt Matoy

Daniel Pedone

Mario Barusic

Andreas Behrendt

Georg Schinner

Muhammad Muhammat Sanusi

Nurfarena Othman

Daniel Bolowski

Marian Sebastian Broll

Stephan Henneck

Michael Kreuz

Peter Imrich

Reinhard Lindner

Norbert Pielmeier

Chin Yung Lai

Siew Ching Seah

Gert Pfahl

Sandra Wirtitsch

Aleksander Hinz

Simon Faiss

A method of manufacturing a semiconductor device includes forming a wiring metal layer structure; forming a dielectric layer structure arranged directly on the wiring metal layer structure; and forming a bonding pad metal layer structure arranged, at least partially, directly on the dielectric layer structure, wherein a layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure, wherein the wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

Semiconductor device including bonding pad metal layer structure

A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.

Chip package and method of forming a chip package

A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.

Semiconductor device including a solder compound containing a compound Sn/Sb

A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.

Electronic device, electronic module and methods for fabricating the same

A semiconductor device and a method of producing the semiconductor device are described. The semiconductor device includes: a semiconductor substrate; a metallization layer over the semiconductor substrate; a plating over the metallization layer, the plating including NiP; a passivation over the metallization layer and laterally adjacent the plating such that a surface of the plating that faces away from the semiconductor substrate is uncovered by the passivation, wherein a seam is present along an interface between the passivation and the plating; and a structure that covers the seam along a periphery of the plating and delimits a bondable area for the plating. The structure extends from the periphery of the plating onto the passivation. The structure includes an imide having a curing temperature below a recrystallization temperature of the NiP or an oxide having a deposition temperature below the recrystallization temperature of the NiP.

Semiconductor device and method of producing a semiconductor device

A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280&#xb0; C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40&#xb0;.

Method of forming an aluminum oxide layer, metal surface with aluminum oxide layer, and electronic device

A semiconductor substrate has a bond pad. The bond pad includes a layer of an aluminum alloy having a chemical composition including at least 0.3% by weight of at least one of Zn, Mg, Sc, Zr, Ti, Ag and/or Mn, with the balance being at least Al and incidental impurities.

Semiconductor substrate having a bond pad material based on aluminum

A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.

Component and method of manufacturing a component using an ultrathin carrier

A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.

Chip arrangements

A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 &#x3bc;m to 10 &#x3bc;m. A method of manufacturing a metal surface with such micropores also is described.

Porous Cu on Cu surface for semiconductor packages

A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.

Solder metallization stack and methods of formation thereof

Growing community of inventors

Diex, Austria

Evelyn Napetschnig