International Business Machines Corporation

Evanthia Papadopoulou

Daniel Nelson Maynard

Robert J Allen

Mervyn Y Tan

Sarah C Braasch

Mervyn Yee-Min Tan

Mark Alan Lavin

Jason D Hibbeler

Sani Richard Nassif

Ruchir Puri

Gustavo Enrique Tellez

Rouwaida N Kanj

Kevin W McCullen

Hua Xiang

Robert F Walker

Louise Helen Trevillyan

Matthew Thomas Guzowski

Archibald John Allen

Der-Tsai Lee

Sarah C Prue

Peter K Chan

Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.

Critical area computation of composite fault mechanisms using Voronoi diagrams

Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample.

Method and system for analyzing an integrated circuit based on sample windows selected using an open deterministic sequencing technique

A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.

Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design

A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.

IC design modeling allowing dimension-dependent rule checking

An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.

System and method for global circuit routing incorporating estimation of critical area estimate metrics

In one embodiment, the present invention is a method and apparatus for net-aware critical area extraction. One embodiment of the inventive method for determining the critical area of an integrated circuit includes modeling a net corresponding to the integrated circuit as a graph, where the net is made up of a plurality of interconnected shapes spanning one or more layers of the integrated circuit. All generators for opens are then defined and identified. The Voronoi diagram of the identified generators is computed, and the critical area is computed in accordance with the Voronoi diagram.

Method and apparatus for net-aware critical area extraction

Method, system and program product for determining a critical area in a region of an integrated circuit layout using Voronoi diagrams and shape biasing. The method includes the steps of generating a biased Voronoi diagram based on a layout geometry of the region and incorporating a shape bias; and determining the critical area for the region using the biased Voronoi diagram.

Integrated circuit layout critical area determination using Voronoi diagrams and shape biasing

Critical area computation of composite fault mechanisms using voronoi diagrams

A method for computing critical area for opens of a layout, which may be implemented by program storage device readable by machine, tangibly embodying a program of instructions executable by the machine, to perform the method steps includes computing Voronoi diagrams of shapes of the layout, determining core elements and weights for the core elements of the shapes, computing a weighted Voronoi diagram for the layout to arrive at a partitioning of the layout into regions, computing critical area within each region and summing the critical areas to arrive at a total critical area for opens in the layout.

Method and system for determining critical area for circuit layouts

An efficient computer implemented method computes critical area for via blocks in Very Large Scale Integrated (VLSI) circuits. The method is incremental and takes advantage of the hierarchy in the design. In order to increase the efficiency further we use the L,or the L,metric instead of the Euclidean geometry.

Incremental method for critical area and critical region computation of via blocks

A method for computing critical area for shorts of a layout, in accordance with the present invention, includes the steps of computing a Voronoi diagram for the layout, computing a second order Voronoi diagram to arrive at a partitioning of the layout into regions, computing critical area within each region and summing the critical areas to arrive at a total critical area for shorts in the layout. A system is also provided for calculating the critical area.

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Evanthia Papadopoulou