Advanced Micro Devices Corporation

Qualcomm Incorporated

Evandro Carlos Menezes

Morrie Altmejd

David Francis Tobias

Richard G Russell

Dave Tobias

Lucian Codrescu

Erich Plondke

Suresh Kumar Venkumahanti

Charles Joseph Tabony

Ajay Anant Ingle

Harsha Jagasia

Erich James Plondke

An integrated circuit includes a plurality of functional blocks. Utilization information for the various functional blocks is generated. Based on that information, the power consumption and thus the performance levels of the functional blocks can be tuned. Thus, when a functional block is heavily loaded by an application, the performance level and thus power consumption of that particular functional block is increased. At the same time, other functional blocks that are not being heavily utilized and thus have lower performance requirements can be kept at a relatively low power consumption level. Thus, power consumption can be reduced overall without unduly impacting performance.

Performance and power optimization via block oriented performance measurement and control

Systems and methods for tracking and switching between execution modes in processing systems. A processing system is configured to execute instructions in at least two instruction execution triodes including a first and second execution mode chosen from a classic/aligned mode and a compressed/unaligned mode. Target addresses of selected instructions such as calls and returns are forcibly misaligned in the compressed mode, such one or more bits, such as, the least significant bits (alignment bits) of the target address in the compressed mode are different from the corresponding alignment bits in the classic mode. When the selected instructions are encountered during execution in the first mode, a decision to switch operation to the second mode is based on analyzing the alignment bits of the target address of the selected instruction.

Using the least significant bits of a called function's address to switch processor modes

An apparatus includes a memory that stores an instruction including an opcode and an operand. The operand specifies an immediate value or a register indicator of a register storing the immediate value. The immediate value is usable to identify a function call address. The function call address is selectable from a plurality of function call addresses.

Table call instruction for frequently called functions

A transaction is sent over a communication link to a receiving node. The transaction includes data along with a tag identifying a data type of the data. The receiving node either forwards or processes the data according to whether the data type matches the type of data type processed by circuitry associated with the receiving node. Thus, a destination is determined for data transported on the communication link using a data type identifier sent with the data.

Data stream labeling and processing

A computer system has multiple performance states. The computer system periodically determines utilization information for the computer system and adjusts the performance state according to the utilization information. If a performance increase is required, the computer system always goes to the maximum performance state. If a performance decrease is required, the computer system steps the performance state down to a next lower performance state.

Method and apparatus for improving responsiveness of a power management system in a computing device

An information processing system is configured to schedule tasks to a plurality of processors using processor performance information. For example, the maximum performance level of each of the processors, the current performance level of each of the processors, and the number of processors can be used to schedule tasks to one or more of the processors. A task distribution frequency which takes this information into account can be useful. One such task distribution frequency fis calculated so that f=D/&#x3a3;Dwhere i ranges from 1-N and D=MP/CP/N, where MPis a maximum performance level for the processor i, CPis a current performance level for the processor i, and N is the number of processors. Tasks are distributed according to the task distribution frequency f.

Multi-processor task scheduling

System and method for controlling an intergrated circuit to enter a predetermined performance state by skipping all intermediate states based on the determined utilization of the intergrated circuit

A task queue management technique leverages infrastructure provided by file and operating systems to manage task queues substantially without otherwise typical problems regarding management of the size of the queue and/or the state of the queue (e.g., empty or full) while maintaining, regulating and altering the queue and the order of tasks in the queue. Task producer code is configurable to cause one or more executable files corresponding to each of one or more tasks to be stored in a queue directory responsive to receiving the one or more tasks. A file system associates each executable file with a time stamp indicating when the executable file was stored. Task consumer code is configurable to execute the one or more executable files in an order indicated by the time stamps associated with the executable files and to remove each executable file after execution of each executable file.

File system based task queue management

A dependency instruction encodes dependency information among a group of instructions. A processor decodes the dependency instruction associated with the group of instructions. The processor can then execute the group of instructions in an order based on the dependency information in the dependency instruction. The dependency information may be encoded in a neutral instruction so processors that do not support dependency instructions can execute a program containing them.

Use of a neutral instruction as a dependency indicator for a set of instructions

A computer system that has multiple performance states periodically obtains utilization information for a plurality of tasks operating on the processor and determines processor utilization according to the utilization information for the plurality of tasks. The system compares the processor utilization to at least one threshold and selectively adjusts a current processor performance state to another performance state according to the comparison.

CPU utilization measurement techniques for use in power management

A computer system has multiple performance states. The computer system periodically determines if the software power state maintained by power management software that represents the power state of the processor or other computer system component matches the actual power state of the processor or other computer system component. If not, the actual power state and the software power state are resynchronized, for example, by reinitializing the power management software or otherwise causing the software power state to match the hardware power state.

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Austin, TX, United States of America

Evandro Carlos Menezes