Google Inc.

Evan Jeffrey

Julian Shaw Kelly

Joshua Yousouf Mutus

Daniel Thomas Sank

Ofer Naaman

Rami Barends

Anthony Edward Megrant

Theodore Charles White

Paul Victor Klimov

Charles Neill

Amit Vainsencher

Christopher Michael Quintana

Paul Kimov

A method of fabricating a carrier chip for distributing signals among circuit elements of a quantum computing device, includes: providing a multilayer wiring stack, the multilayer wiring stack comprising alternating layers of dielectric material and wiring; bonding a capping layer to the multilayer wiring stack, in which the capping layer includes a single crystal silicon dielectric layer; forming a via hole within the capping layer, in which the via hole extends to a first wiring layer of the multilayer wiring stack; forming an electrically conductive via within the via hole and electrically coupled to the first wiring layer; and forming a circuit element on a surface of the capping layer, in which the circuit element is directly electrically coupled to the electrically conductive via.

Signal distribution for a quantum computing system

A quantum computing device includes: a qubit; a single XYZ control line, in which the qubit and the single control line are configured and arranged such that, during operation of the quantum computing device, the single XYZ control line allows coupling of an XY qubit control flux bias, from the single XYZ control line to the qubit, over a first frequency range at a first predetermined effective coupling strength, and coupling of a Z qubit control flux bias, from the single XYZ control line to the qubit, over a second frequency range at a second predetermined effective coupling strength.

Single line qubit control

A cryogenic cooling system for use in quantum computing applications can include a plurality of cryogenic cooling stages. Each of the plurality of cryogenic cooling stages can include a plurality of interleaved cooling units. The plurality of interleaved cooling units can include a first cooling unit and a second cooling unit. Each of the plurality of interleaved cooling units can have an associated operating temperature range. One or more signal lines that couple one or more classical processors to one or more quantum systems can pass through each of the plurality of interleaved cooling units for each of the plurality of cryogenic cooling stages.

Interleaved cryogenic cooling system for quantum computing applications

This disclosure is directed to a quantum computing system (QCS) that includes a cryogenic sub-system, a signal-generating element, a first signal-splitting element, a first transmission path, a second transmission path, a third transmission path, and a quantum device. A first environment is located outside the cryogenic sub-system and a second environment is associated with the cryogenic sub-system. The signal-generating element generates a first signal. The first signal-splitting element is positioned within the second environment. The quantum device is positioned within the cryogenic sub-system. The first transmission path transmits the first signal from the signal-generating element to the first signal-splitting element. The first signal-splitting element subdivides the first signal into a second signal and a third signal. The third transmission transmits the third signal from the first signal-splitting element to the first environment. The second transmission path transmits the second signal from the first signal-splitting element to the quantum device.

Thermalization and attenuation of signals within quantum computing systems via directional couplers

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for parameterization of physical dimensions of discrete circuit components for component definitions that define discrete circuit components. The component definitions may be selected for use in a device design. When a parametrization of a particular version of a discrete circuit component definition is changed, the version level of the device design is also changed and the circuit layout for the device design is physically verified for the new version level.

Integrated circuit design system and method

A device includes a first substrate having a principal surface; a second substrate having a principal surface, in which the first substrate is bump-bonded to the second substrate such that the principal surface of the first substrate faces the principal surface of the second substrate; a circuit element having a microwave frequency resonance mode, in which a first portion of the circuit element is arranged on the principal surface of the first substrate and a second portion of the circuit element is arranged on the principal surface of the second substrate; and a first bump bond connected to the first portion of the circuit element and to the second portion of the circuit element, in which the first superconductor bump bond provides an electrical connection between the first portion and the second portion.

Low footprint resonator in flip chip geometry

A device includes: a first chip including a plurality of qubits arranged in an array on a first side of the first chip, in which the array includes a plurality of qubit rows and a plurality of qubit columns, in which the plurality of qubits includes a first qubit row including two or more qubits and a second qubit row including two or more qubits, and in which the second qubit row is directly adjacent to the first qubit row; a second chip bonded to the first chip, in which the second chip has a first side that faces the first side of the first chip; a plurality of qubit control elements; a plurality of qubit readout resonators; and a plurality of qubit readout transmission lines.

Scalable quantum processor design

A quantum processor includes: a first chip comprising a qubit array, in which a plurality of qubits within the qubit array define an enclosed region on the first chip, in which each qubit of the plurality of qubits that define the enclosed region is arranged to directly electromagnetically couple to an adjacent qubit of the plurality of qubits that define the enclosed region, and in which each qubit of the qubit array comprises at least two superconductor islands, and a second chip bonded to the first chip, the second chip including one or more qubit control elements, in which the qubit control elements are positioned directly over the enclosed region of the first chip.

Quantum processor design to increase control footprint

A circuit is presented which includes a first amplifier having an input, a transmission line having first and second ends. The first end of the transmission line is coupled to an input of the first amplifier and a plurality of channels. Each channel includes a plurality of resonators arranged to read out a plurality of qubits, respectively and a readout line arranged to receive read out signals from the plurality of resonators. The readout line of each channel is coupled to the transmission line and each channel is configured to output a respective signal in a respective frequency band which is different from frequency bands of other channels in the plurality of channels.

Multiplexed readout system

An apparatus includes: a transmission line resonator; and multiple resonators coupled to the transmission line resonator, in which each resonator of the multiple resonators is coupled to the transmission line resonator at a different position X along a length of the transmission line resonator, and in which, for each resonator of the multiple resonators, a coupling position Y along a length of the resonator is selected such that, upon application of a source potential to the resonator, a standing wave established in the resonator is impedance and phase matched to a standing wave established in the transmission line resonator.

Growing community of inventors

Santa Barbara, CA, United States of America

Evan Jeffrey