Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Eunjung Kim

Yoosang Hwang

Bong-Soo Kim

Keunnam Kim

Daeik Kim

Hui-Jung Kim

Sohyun Park

Jay-Bok Choi

Hyungbin Cho

Hyewon Kim

Kiseok Lee

Yongman Park

Dong-Wan Kim

Taewoo Kim

Jemin Park

Seung-Won Park

Junghoon Han

Gugrae Jo

Daehwan Jang

Semyeong Jang

Yongseok Ahn

Sungyeon Ryu

Sangho Lee

Sang-Hoon Lee

Miyeon Park

Hyun-Seok Kim

Yoonyoung Choi

Eun Ah Kim

Yunjong Yeo

Yong Kwan Kim

Myeong-Dong Lee

Sangyeon Han

Yong-Hwan Ryu

GeumJung Seong

Heewon Kang

Kyung-Eun Kim

Junhyeok Ahn

Eunhye Jee

Myungkwang Byun

Ki-Hyung Nam

Hyo-Sub Kim

Youbi Seo

Hwayoun Suh

Hyo Joon Kim

Moonjung An

Seon-tae Yoon

Hyunju Kang

Sung-Young Choi

Hyunyong Kim

Jihun Kim

Baehyoun Jung

Jeongseop Shim

Hyochul Kwak

Byung Yoon Kim

Sei-ryung Choi

The according to an embodiment includes a substrate, a transistor disposed on the substrate, a light-emitting device electrically connected to the transistor, an encapsulation layer disposed on the light-emitting device, a partition wall disposed on the encapsulation layer and including an opening overlapping the light-emitting device, and a color converting layer, a low-refractive index layer, and a color filter sequentially stacked on each other in the opening.

Display device having color filters and partition and method for manufacturing the same

Provided is a semiconductor memory device comprising a device isolation pattern in a substrate and defining first and second active sections spaced apart from each other, wherein a center of the first active section is adjacent to an end of the second active section, a bit line that crosses over the center of the first active section, a bit-line contact between the bit line and the first active section, and a first storage node pad on the end of the second active section. The first storage node pad includes a first pad sidewall and a second pad sidewall. The first pad sidewall is adjacent to the bit-line contact. The second pad sidewall is opposite to the first pad sidewall. When viewed in plan, the second pad sidewall is convex in a direction away from the bit-line contact.

Semiconductor memory device

A semiconductor memory device includes active patterns spaced apart from each other in first and second directions intersecting each other, each active pattern having a central portion, a first end portion, and a second end portion, bit line contacts disposed on the central portions and spaced apart from each other in the first and second directions, separation insulating patterns, each of which is disposed between the bit line contacts adjacent to each other in the first and second directions, intermediate insulating patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the first direction, and connection patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the second direction.

Semiconductor memory device having connection pattern between the bit line contact and the separation insulating pattern

A semiconductor memory device includes a device isolation pattern on a substrate and defining a first active section, a first storage node pad on the first active section, a word line in the substrate and extending across the first active section, a bit line on the first storage node pad and crossing over the word line, a storage node contact on one side of the bit line and adjacent to the first storage node pad, and an ohmic layer between the storage node contact and the first storage node pad. A bottom surface of the ohmic layer is rounded.

Semiconductor memory device and method of fabricating the same

Disclosed are a semiconductor device and a method of fabricating the same. In the semiconductor device, a supporting pattern may be used to fix upper portions of active patterns, when a gap-filling process is performed to fill a region between active patterns, and thus, it may be possible to prevent or reduce the likelihood of the active patterns from being bent or fallen. Thus, it may be possible to reduce failure of the semiconductor device and/or to improve reliability of the semiconductor device.

Semiconductor devices and methods of fabricating the same

A semiconductor device includes a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region, cell active patterns on the cell region of the substrate, peripheral active patterns on the peripheral region of the substrate, a boundary insulating pattern disposed on the boundary region of the substrate and disposed between the cell active patterns and the peripheral active patterns, and a bumper pattern disposed on the cell region of the substrate and disposed between the boundary insulating pattern and the cell active patterns. A width of the bumper pattern in a first direction parallel to a top surface of the substrate is greater than a width of each of the cell active patterns in the first direction.

Semiconductor devices

A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

A semiconductor device includes a substrate including a cell region, a peripheral region, and a boundary region therebetween, a cell device isolation pattern on the cell region of the substrate to define cell active patterns, a peripheral device isolation pattern on the peripheral region of the substrate to define peripheral active patterns, and an insulating isolation pattern on the boundary region of the substrate, the insulating isolation pattern being between the cell active patterns and the peripheral active patterns, wherein a bottom surface of the insulating isolation pattern includes a first edge adjacent to a side surface of a corresponding one of the cell active patterns, and a second edge adjacent to a side surface of a corresponding one of the peripheral active patterns, the first edge being at a height lower than the second edge, when measured from a bottom surface of the substrate.

Semiconductor device and method of fabricating the same

A method of manufacturing a roll type imprint master mold including disposing a base layer on a substrate including a first area and a second area adjacent to the first area, disposing an inorganic insulation layer on the base layer, forming a first mask pattern and a first resin pattern in the first area, forming a pattern layer by etching the inorganic insulation layer using the first resin and the first mask patterns as a mask, removing the first resin and the first mask patterns, forming a second mask pattern and a second resin pattern in the second area, forming a pattern layer by etching the inorganic insulation layer using the second resin and the second mask patterns as a mask, removing the second resin and the second mask patterns, separating the base layer from the substrate, and attaching the base layer onto a roll body.

Roll type imprint master mold, method of manufacturing the same, and imprint method using the same

Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises forming an active structure including a plurality of active patterns, a device isolation layer defining the active patterns, and a gate structure across the active patterns and extending in a first direction, forming a first mask pattern on the active structure, and forming a trench by using the first mask pattern as an etching mask to pattern the active structure. Forming the first mask pattern comprises forming in a first mask layer a plurality of first openings extending in a second direction intersecting the first direction, and forming in the first mask layer a plurality of second openings extending in a third direction intersecting the first and second directions.

Semiconductor device and method of manufacturing the same

A method of fabricating a semiconductor memory device includes forming a bit line and a bit line capping pattern on the semiconductor substrate, forming a first spacer covering a sidewall of the bit line capping pattern and a sidewall of the bit line, forming a contact plug in contact with a sidewall of the first spacer and having a top surface that is lower than an upper end of the first spacer, removing an upper portion of the first spacer, forming a first sacrificial layer closing at least an entrance of the void, forming a second spacer covering the sidewall of the bit line capping pattern and having a bottom surface in contact with a top surface of the first spacer, and removing the first sacrificial layer. The bit line capping pattern is on the bit line. The contact plug includes a void exposed on the top surface.

Methods of fabricating semiconductor memory devices

Growing community of inventors

Daegu, South Korea

Eunjung Kim